Boyan Boyanov

Tri-Gate fully-depleted CMOS transistors: fabrication, design and layout

Tri-Gate fully-depleted CMOS transistors have been fabricated with various body dimensions. These experimental results and 3-D simulations are used to explore the design space for full depletion, as well as layout issues for the Tri-Gate architecture, down to 30 nm gate lengths. It is found not only that the Tri-Gate body dimensions are flexible and relaxed compared to single-gate or double-gate devices, but that the corner plays a fundamental role in determining the device I-V characteristics. The corner device not only turns on at lower voltages due to the proximity of two adjacent gates, but the DIBL of this part of the device is much smaller than the rest of the transistor. The shape of the subthreshold I-V characteristics and the degree of DIBL control, as well as the early device turn-on are also greatly affected by the degree of body corner rounding. Examination of layout issues shows that the fin-doubling approach from using a spacer printing technique results in an increase in drive current of 1.2 times that of a planar device for a given width, though the shape of the allowed Tri-Gate fins has certain restrictions.

Silicon nano-transistors for logic applications

Abstract Silicon transistors have undergone rapid miniaturization in the past several decades. Recently reported CMOS devices have dimensional scales approaching the “nano-transistor” regime. This paper discusses performance characteristics of a MOSFET device with 15 nm physical gate length. In addition, aspects of a non-planar CMOS technology that bridges the gap between traditional CMOS and the nano-technology era will be presented. It is likely that this non-planar device will form the basic device architecture for future generations of nano-technology.

On‐Wafer Crystallization of Ultralow‐κ Pure Silica Zeolite Films

A higher goal: An on-wafer crystallization process to prepare pure silica zeolite (PSZ) MEL-type films that is superior to the previously used hydrothermal process is reported. These striation-free MEL-type films (right, see picture) outperform the traditional spin-on films (left) in terms of the kappa value, mechanical properties, surface roughness, mesopore size, and size distribution.

Contacting nanowires and nanotubes with atomic precision for electronic transport

Making contacts to nanostructures with atomic precision is an important process in the bottom-up fabrication and characterization of electronic nanodevices. Existing contacting techniques use top-down lithography and chemical etching, but lack atomic precision and introduce the possibility of contamination. Here, we report that a field-induced emission process can be used to make local contacts onto individual nanowires and nanotubes with atomic spatial precision. The gold nano-islands are deposited onto nanostructures precisely by using a scanning tunneling microscope tip, which provides a clean and controllable method to ensure both electrically conductive and mechanically reliable contacts. To demonstrate the wide applicability of the technique, nano-contacts are fabricated on silicide atomic wires, carbon nanotubes, and copper nanowires. The electrical transport measurements are performed in situ by utilizing the nanocontacts to bridge the nanostructures to the transport probes.

Insight into on-wafer crystallization of pure-silica-zeolite films through nutrient replenishment.

Tetraethylorthosilicate (TEOS) is added to a pure-silica-zeolite MEL nanoparticle suspension and the mixture is subsequently used for preparing spin-on low-dielectric constant (low-k) films. The films are then characterized by ellipsometric porosimetry, transmission electron microscopy (TEM), and nanoindentation. Investigation into the film microstructure indicates that the addition of TEOS significantly increases the fraction of the crystalline domains, decreases the inter-crystal mesopore size, and narrows the pore size distribution. Films with 12% TEOS loading have a mean pore size distribution centered at 3.5 nm (diameter) with a full width at half maximum (fwhm) of 0.8 nm, while those with no TEOS have a distribution at 11.1 nm and fwhm of 7.9 nm. At 12% TEOS loading, the reduced modulus and hardness are 11.0 and 1.12 GPa, respectively; without TEOS, the values are 6.4 and 0.57 GPa.