Shaofeng Yu

New insights into AC RTN in scaled high-к / metal-gate MOSFETs under digital circuit operations

Since devices actually operate under AC signals in digital circuits, it is more informative to study random telegraph noise (RTN) at dynamic AC biases than at constant DC voltages. We found that the AC RTN statistics largely deviates from traditional DC RTN, in terms of different distribution functions and the strong dependence on AC signal frequency, which directly impacts on the accurate prediction of circuit stability and variability. The AC RTN characteristics in high-κ/metal-gate FETs are different from that in SiON FETs, and both of which cannot be described by classical RTN theory. A physical model based on quantum mechanics is proposed, which successfully explains the new observations of AC RTN. It is also demonstrated that, if using DC RTN statistics instead of AC RTN, a large error of 30% overestimation on the read failure probability in ultra-scaled SRAM cells will occur. These new understandings are critical for the robust circuit design against RTN in practical digital circuits.

New observations on AC NBTI induced dynamic variability in scaled high-κ/Metal-gate MOSFETs: Characterization, origin of frequency dependence, and impacts on circuits

In this paper, the frequency dependence of the dynamic variation induced by AC NBTI aging in scaled high-κ/metal-gate devices are experimentally studied for the first time. Challenges in comprehensively characterizing AC NBTI induced variation are addressed by the modified method. The additional variation source in AC NBTI, originating from the variations among each AC clock cycle, is found to be non-negligible and thus should be included in predicting circuit stability. With increasing AC frequency, the mean value (μ) of the Vth shift (ΔVth) is reduced as expected; however, the variation (σ) of ΔVth is almost unchanged, which surprisingly disagrees with the conventional model predicting the reduced variation. The origin of this new observation is found due to the competitive impacts of the activated trap number and the trap occupancy probability during device aging. Taken clock-CCV and frequency dependence into account, the impacts of AC NBTI on the SRAM cell stability can be evaluated in terms of both degradation and variation. The results are helpful for the future variability-aware circuit design.

New insights into the design for end-of-life variability of NBTI in scaled high-κ/metal-gate Technology for the nano-reliability era

In this paper, a new methodology for the assessment of end-of-life variability of NBTI is proposed for the first time. By introducing the concept of characteristic failure probability, the uncertainty in the predicted 10-year VDD is addressed. Based on this, variability resulted from NBTI degradation at end of life under specific VDD is extensively studied with a novel characterization technique. With the further circuit level analysis based on this new methodology, the timing margin can be relaxed. The new methodology has also been extended to FinFET in this work. The wide applicability of this methodology is helpful to future reliability/variability-aware circuit design in nano-CMOS technology.

New understanding of state-loss in complex RTN: Statistical experimental study, trap interaction models, and impact on circuits

In this paper, the statistical characteristics of complex RTN (both DC and AC) are experimentally studied for the first time, rather than limited case-by-case studies. It is found that, over 50% of RTN-states predicted by conventional theory are lost in actual complex RTN statistics. Based on the mechanisms of non-negligible trap interactions, new models are proposed, which successfully interpret this state-loss behavior, as well as the different complex RTN characteristics in SiON and high-κ devices. The circuit-level study also indicates that, predicting circuit stability would have large errors if not taking into account the trap interactions and RTN state-loss. The results are helpful for the robust circuit design against RTN.

Adding the missing time-dependent layout dependency into device-circuit-layout co-optimization — New findings on the layout dependent aging effects

In this paper, a new class of layout dependent effects (LDE)-the time-dependent layout dependency due to device aging, is reported for the first time. The BTI and HCI degradation in nanoscale HKMG devices are experimentally found to be sensitive to layout configurations, even biased at the same stress condition. This new effect of layout dependent aging (LDA) can significantly mess the circuit design, which conventionally only includes the static LDE modeled for time-zero performance. Further studies at circuit level indicate that, for resilient device-circuit-layout co-design, especially to ensure enough design margin near the end of life, LDA cannot be neglected. The results are helpful to guide the cross-layer technology/design co-optimization.

Deep insights into dielectric breakdown in tunnel FETs with awareness of reliability and performance co-optimization

The gate dielectrics reliability in Tunnel FETs (TFETs) has been thoroughly investigated for the first time, which is found to be the dominant device failure mechanism compared with bias temperature ins tability degradation, and is much worse than MOSFETs with the same gate stacks due to a new stronger localized dielectric field peak at gate/source overlap region. The non-uniform electric field of dielectric in TFET also leads to the different mechanisms between soft breakdown and hard breakdown failure. Moreover, dielectric-field-associated parameters are discussed in detail, showing an intrinsic trade-off between dielectrics reliability and device performance optimization caused by the positive correlation between dielectric field and source junction field. A new robust design consideration is further proposed for reliability and performance co-optimization, which is experimentally realized by a new TFET design with both dramatically improved performance and reliability, indicating its great potentials for ultralow-power applications.

Process optimization for random threshold voltage variation reduction in nanoscale MOSFET by 3D simulation

Process optimization strategy to reduce random threshold voltage (Vt) variation for CMOS at 65 nm and beyond is presented. The impact of related process parameters such as halo/Vt implant species, energy and dosage on Vt mismatch are analyzed and compared by 3D TCAD simulation. It is revealed that the random dopant fluctuation (RDF) can be dramatically suppressed by carbon implant with sufficient dosage combines proper energy. Besides, Vt tuning and halo implants by indium is recommended because it is less susceptible to Vt variation than Bf2. All these results of process optimization can be well explained by the shift of impurity doping level near the surface.

A novel method for accurate measurement and decoupling of SRAM standby leakage

A novel method for SRAM cell standby leakage measurement is presented, which enables accurate testing and decoupling of sub-threshold leakage (I_sub), gate leakage (I_gate) and junction leakage (I_junc) in each SRAM cell transistor. Moreover, the array based technique can not only precisely measure small current but also compensate the impact from random variations. The front-end SRAM array layout is kept original to preserve actual physical environment. The method is verified in SMIC 65nm technology. The data of I_sub, I_gate and I_junc of pull-down (PD), pull-up (PU) and pass-gate (PG) transistor are collected for process optimization to reduce standby power.