Krishnamurthy Soumyanath

A sub-130-nm conditional keeper technique

Increasing leakage currents combined with reduced noise margins significantly degrade the robustness of wide dynamic circuits. In this paper, we describe two conditional keeper topologies for improving the robustness of sub-130-nm wide dynamic circuits. They are applicable in normal mode of operation as well as during burn-in test. A large fraction of the keepers is activated conditionally, allowing the use of strong keepers with leaky precharged circuits without significant impact on performance of the circuits. Compared to conventional techniques, up to 28% higher performance has been observed for wide dynamic gates in a 130-nm technology. In addition, the proposed burn-in keeper results in 64% active area reduction.

Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/

This paper describes an experiment to characterize soft error rate of static latches for neutrons using a neutron beam, with measured soft error rates as a function of diffusion collection areas and supply voltages. The paper also quantifies the effectiveness of two promising hardening techniques and scaling trends.

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.

A four-antenna receiver in 90-nm CMOS for beamforming and spatial diversity

A fully integrated four-channel multi-antenna receiver intended for beamforming and spatial diversity applications is presented. It can also be used as a low-power area-efficient range extender for spatially multiplexed multi-antenna systems that are poised to become mainstream in the near future. Implemented in a 90-nm CMOS technology, each channel weights its input signal by a complex weight with full 360/spl deg/ phase shift programmability using vector combinations of variable-gain amplifiers, thus obviating the need for expensive phase shifters. The chip consumes 140 mW from a single 1.4-V supply and achieves 12 dB of array gain with all four channels activated and >20 dB direction-of-arrival-dependent interference rejection.

A 64 GHz LNA With 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS

This paper presents an integrated LNA for millimeter-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for ldquocorrect-by-constructionrdquo design at mm-wave frequencies and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with a NF of 6.5 dB, while drawing 26mA per stage from 1.65 V. Output is 3.8 dBm. At , each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB, respectively. Measured results are in excellent agreement with simulations, proving the effectiveness of the proposed design methodology. A custom set-up for mm-wave NF measurement is also extensively described in the paper.

A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS

A class-E power amplifier (PA) utilizes differential switches and a tuned passive output network improves power-added efficiency (PAE) and insensitivity to amplitude variations at its input. A modulator is introduced that takes outphased waveforms as its inputs and generates a pulse-width and pulse-position modulated (PWPM) signal as its output. The PWPM modulator is used in conjunction with a class-E PA to efficiently amplify constant envelope (e.g., GMSK) and non-constant envelope (e.g., QPSK, QAM, OFDM) signals with moderate peak-to-average ratios (PAR). The measured maximum output power of the PA is 28.6 dBm with a PAE of 28.5%, and the measured error vector magnitude (EVM) is 1.2% and 4.6% for GMSK and pi/4-DQPSK (PAR ap 4 dB) modulated signals, respectively.

A Flip-Chip-Packaged 25.3 dBm Class-D Outphasing Power Amplifier in 32 nm CMOS for WLAN Application

A 2.4 GHz outphasing power amplifier (PA) is implemented in a 32 nm CMOS process. An inverter-based class-D PA topology is utilized to obtain low output impedance and good linearity in the outphasing system. MOS switch non-idealities, such as finite on-resistance and finite rise and fall times are analyzed for their impact on outphasing linearity and efficiency. Outphasing combining is performed via a transformer configured to achieve reduced loss at power backoff. The fabricated class-D outphasing PA delivers 25.3 dBm peak CW power with 35% total system Power Added Efficiency (includes all drivers). Average OFDM power is 19.6 dBm with efficiency 21.8% when transmitting WiFi signals with no linearization required. The PA is packaged in a flip-chip BGA package. Good linearity performance (ACPR and EVM) demonstrates the applicability of inverter-based class-D amplifiers for outphasing configurations.

A 130-nm 6-GHz 256 /spl times/ 32 bit leakage-tolerant register file

Describes a 256-word /spl times/ 32-bit 4-read, 4-write ported register file for 6-GHz operation in 1.2-V 130-nm technology. The local bitline uses a pseudostatic technique for aggressive bitline active leakage reduction/tolerance to enable 16 bitcells/bitline, low-V/sub t/ usage, and 50% keeper downsizing. Gate-source underdrive of -V/sub cc/ on read-select transistors is established without additional supply/bias voltages or gate-oxide overstress. 8% faster read performance and 36% higher dc noise robustness is achieved compared to dual-V/sub t/ bitline scheme optimized for high performance. Device-level measurements in the 130-nm technology show 703/spl times/ bitline active leakage reduction, enabling continued V/sub t/ scaling and robust bitline scalability beyond 130-nm generation. Sustained performance and robustness benefit of the pseudostatic technique against conventional dynamic bitline with keeper-upsizing is also presented.

A 1.05 V 1.6 mW, 0.45

Monitoring temperature in a microprocessor is important for optimal energy consumption under various workloads. This paper presents a temperature sensor in a 32 nm high-k metal gate digital CMOS process for integration in a microprocessor core. The sensor uses a ratio of currents driven into a BJT pair with current chopping to up-convert the temperature signal. A second order sigma-delta (ΣΔ) 1-bit ADC is used to digitize the chopped signal, which is then down-converted and filtered in the digital domain to obtain a temperature measurement. The sensor operates from -10 to 110°C, achieving a 3σ resolution of 0.45°C, and ≪5°C inaccuracy without calibration/trimming.

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This paper describes an on-chip sampling and measurement technique for accurate (<15 ps) evaluation of interconnect delays and coupled noise. We have used this nonintrusive time-domain technique to extract in situ driver/receiver waveforms, propagation delays, and coupled noise in 120 interconnect structures. The effects studied include multiple AC returns through active devices, gridded planes on adjacent layers, via impedances, variable driver impedances, and noise in bus structures. The results provide a comprehensive evaluation of interconnect delays and noise in a 1.8 V, 0.25 /spl mu/m process.