Brian A. Winstead

Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain

The influence of tensile mechanical stress on ultrathin oxide gate currents in advanced partially depleted silicon-on-insulator MOSFETs is reported. Strain is applied uniaxially, perpendicular to the direction of current flow by bending of thinned, fully processed wafers with a gate oxide thickness of less than 1.5 nm. The gate currents of the n-channel and p-channel MOSFETS are found to change linearly and in opposite (opposing) directions as a function of uniaxial strain. The nMOS transistors generally exhibit a decrease with applied tensile strain, while the nMOS transistors show increasing gate current with strain. The observed dependences are consistent with a gate current controlled by direct tunneling and perturbed by stress-induced changes in the energy band structure.

Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High-

Achieving low p-channel metal-oxide-semiconductor (PMOS) threshold voltages with metal gates and high-k dielectrics is challenging with conventional gate-first complimentary metal-oxide-semiconductor process integration. This study, for the first time, explores the tradeoffs in using different combinations of thin-strained Si1 - x Gex channels, boron counterdopings, Si capping layers, and different metal-gate electrodes to obtain low PMOS threshold voltages with metal gate on high-k dielectrics in a gate-first integration technology. Device simulations are used to explain the experimental threshold voltage trends with varying Si1 - x Gex thicknesses, boron counterdopings, and gate work functions.

k

A theoretical study of the response of hole mobility and thermal velocity, both relevant for short channel devices, to [110] uniaxial stress in Si up to 4 GPa of both tension and compression has been conducted. The strained-Si bandstructure was calculated using the kmiddotp method. Effective masses, thermal velocities, and scattering rates were calculated from the bandstructure as a function of stress. Mobilities were then calculated via full band Monte Carlo simulations. Calculated mobilities match experimental and theoretical data from prior work addressing lower degrees of stress. Large increases in both carrier thermal velocities and mobilities were found. In the high-stress regime between 1 and 2 GPa, mobilities exhibit a strong superlinear dependence, and compressive stress becomes more favorable for increasing both mobilities and thermal velocities in pMOS. Improvements in both thermal velocity and mobility finally only begin to rolloff toward apparent saturation as we push the stress toward 4 GPa in these simulations

Dielectrics

In this paper, we present the first-ever commercially available embedded Microcontrollers built on 90nm-node with silicon nanocrystal memories that has intrinsic capability of exceeding 500K program/erase cycles. We also show that the cycling performance across temperature (-40C to 125C) is very well behaved even while maintaining high performance that meets or exceeds the requirements of consumer, industrial, and automotive markets. In specific EEPROM implementation, such high endurance is capable of delivering in excess of 200M data updates. In addition, we also demonstrate that the nanocrystal flash memory is highly scalable to the next generation nodes and the scaling can be accomplished without degradation of pro-gram/erase speed, endurance and reliability.

Hole Mobility and Thermal Velocity Enhancement for Uniaxial Stress in Si up to 4 GPa

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress

High Performance Nanocrystal Based Embedded Flash Microcontrollers with Exceptional Endurance and Nanocrystal Scaling Capability

Thin SiGe-channel confinement is found to provide significant control of the short channel effects typically associated with nonbandedge gate electrodes, in an analogous manner to ultrathin-body approaches. Gate workfunction requirements for thin-SiGe-channel p-type field effect transistors are therefore relaxed substantially more than what is expected from a simple observation of the difference between gate and channel workfunctions. In particular, thin-SiGe channels are shown to enable cost-effective high-performance bulk CMOS technologies with a single gate workfunction near the conduction bandedge. Buried channel, gate workfunction, metal gate, SiGe-channel confinement effects, SiGe-channel MOSFET, silicon germanium, ultrathin-body (UTB).

Multi-Layer Model for Stressor Film Deposition

This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.

SiGe-Channel Confinement Effects for Short-Channel PFETs With Nonbandedge Gate Workfunctions

The influence of uniaxial tensile strain on the performance of advanced partially depleted silicon-on-insulator CMOS ring oscillators is reported. Strain is applied either perpendicular or parallel to the direction of current flow by bending of thinned, fully processed wafers with a gate oxide thickness of less than 1.5 nm. Interestingly, the standby power dissipation of the ring oscillators increases for both parallel and perpendicular strains due to changes in the gate tunneling currents with strain. The on-state power dissipation decreases with parallel strain and increases with perpendicular strain consistent with the expected changes in the inversion layer piezoresistance. The speed of the ring oscillators improves with perpendicular strain and degrades with parallel strain, which can also be understood in terms of the piezoresistance changes.

16Mb Split Gate Flash Memory with Improved Process Window

Fabrication of current high-performance metal-oxide-semiconductor field effect transistors (MOSFETs) requires a multiple gate oxide integration to obtain different oxide thicknesses and applied voltages. However, channel mobility and drive current are degraded as the number of oxide growth and etching steps increases during the multiple gate oxide integration. In multiple gate oxide integration, a shorter overetch time with a more dilute HF solution for the removal of preexisting oxides exhibits improved surface mobility and transistor drive current resulting from the suppression of surface roughness deterioration. The elimination of SCl cleaning or the addition of a lower-temperature dilute SCl cleaning in the pregate cleaning sequence also produces improved transistor mobility. Considering that the addition of SCl cleaning in the pregate cleaning sequence is needed to remove particles on the surface, the use of a dilute SCl cleaning may be a realistic method to achieve both improvement of transistor performance and removal of particles. Mobility and drive current of nMOSFETs are found to be more sensitive to surface preparation changes than pMOSFETs, which may be explained by the closer proximity of electrons to the Si/SiO 2 interface compared to holes.

Influence of uniaxial tensile strain on the performance of partially depleted SOI CMOS ring oscillators

In this work we perform a study of the data retention behavior of silicon nanocrystalline flash memories. Charge loss is modeled through direct and trap assisted tunneling from the nanocrystals to the channel and to the neighboring nanocrystals. The discrete loss of charge is modeled by a Monte Carlo algorithm. In addition to being more realistic, the Monte Carlo approach, can inherently take into account statistical fluctuations among different memory devices and the effect becomes more important as the devices are scaled down in size. The simulated charge retention data has been fitted to experimental data and show reasonable agreement for various temperatures and oxide thicknesses