Jane A. Yater

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; fast source-side injection programming (10-20 us); fast tunnel erase into the gate; and robust high temperature data retention for both uncycled and cycled arrays. Results presented here with focus on the array operation demonstrate the maturity of this technology for implementation into consumer, industrial, and automotive microcontrollers.

High Performance Nanocrystal Based Embedded Flash Microcontrollers with Exceptional Endurance and Nanocrystal Scaling Capability

In this paper, we present the first-ever commercially available embedded Microcontrollers built on 90nm-node with silicon nanocrystal memories that has intrinsic capability of exceeding 500K program/erase cycles. We also show that the cycling performance across temperature (-40C to 125C) is very well behaved even while maintaining high performance that meets or exceeds the requirements of consumer, industrial, and automotive markets. In specific EEPROM implementation, such high endurance is capable of delivering in excess of 200M data updates. In addition, we also demonstrate that the nanocrystal flash memory is highly scalable to the next generation nodes and the scaling can be accomplished without degradation of pro-gram/erase speed, endurance and reliability.

16Mb Split Gate Flash Memory with Improved Process Window

This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.

A 90nm Embedded 2-Bit Per Cell Nanocrystal Flash EEPROM

A two bit/cell embedded nanocrystal bitcell with low write current SSI program and tunnel erase in which nanocrystals are located under dedicated control gates has been demonstrated. Write bias conditions which mitigate gate disturb in a top erase capable bitcell have been confirmed

Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

In this paper, the authors present the performance characteristics of such a silicon nanocrystal split gate bitcell and report an optimal bitcell process and integration scheme for memory arrays.

An embedded silicon nanocrystal nonvolatile memory for the 90nm technology node operating at 6V

This paper reports on the first functional 6V, 4Mb silicon nanocrystal based nonvolatile memory array using conventional 90nm and 0.25/spl mu/m process technologies. The silicon nanocrystal based NOR Flash can be programmed and erased using conventional techniques in floating gate memories. Key aspects of this technology are the ability to form nanocrystals of the right size and density, the ability to protect them from subsequent processing effects and the ability to remove them from undesired areas. The use of isolated silicon nanocrystals for charge storage provides the opportunity to reduce the program and erase voltages due to tunnel oxide scaling and also has potential for two bits/cell operation. Optimization of tunnel and control oxides is critical to obtain high program/erase cycling endurance. Due to the area savings from memory module peripheral voltage scaling and the reduction in mask count over conventional floating gate technology, silicon nanocrystal non-volatile memory technology can substantially reduce the cost of embedded flash at the 90nm technology node and beyond.

An advanced embedded flash technology for broad market applications

In June 2010, Freescale introduced the Kinetis product family of ARM®-core based 32-bit microcontrollers (MCUs) built on the 90nm TFS (Thin Film Storage) embedded flash technology. That was the first time a flash technology based on the silicon nanocrystals as the storage medium was ever productized - fully 14 years after Tiwari introduced the concept of nanocrystal memory [1]. This paper describes the TFS technology, the architecture, the special features, the robustness, and the extendibility to 40nm and beyond.

Reliability Study of Split Gate Silicon Nanocrystal Flash EEPROM

In this paper, we present a measurement based on biased data retention to determine the direction of charge loss. Top oxide and bottom oxide thickness can be optimized to meet long term reliability goal. A split gate nanocrystal nonvolatile memory with large program window, while demonstrating excellent data retention and program disturb characteristics is also presented.

Optimization of 90nm Split Gate Nanocrystal Non-Volatile Memory

A 90 nm split gate nanocrystal bitcell has been demonstrated with scaled select gate oxide and adjustable control gate threshold voltage that allows for fast, low power SSI operation and top erase. This bitcell performance is excellent and holds promise for embedded flash applications.