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Featured researches published by Brian Moore.


international test conference | 2007

High throughput non-contact SiP testing

Brian Moore; Chris Sellathamby; Philippe Cauvet; Herve Fleury; M. Paulson; Md. Mahbub Reja; Lin Fu; Brenda Bai; Edwin Walter Reid; Igor M. Filanovsky; Steven Slupsky

A non-contact method for parallel testing of system-in-package (SiP) assemblies is presented. This technology allows for JTAG testing of partially or fully populated SiPs in wafer form, in advance of final packaging. The technology utilizes non-contact GHz short-range, near field communications to transfer bi-directional data to SiP substrates; creating a wireless test access port or WTAP. The system is integrated with a standard probe card to deliver power and wireless signals. The wireless probes convert high frequency RF (GHz) transceiver signals to standard tester ATE logic levels and allow the use of standard probers and JTAG testers. In addition, all transceivers (DUTand probe) use antenna structures and electronics that are fully CMOS compliant. Enhancing the economics of SiP manufacture by enabling parallel non-contact testing of SiPs before packaging is a key benefit of this technology.


design, automation, and test in europe | 2009

Contactless testing: possibility or pipe-dream?

Erik Jan Marinissen; Dae Young Lee; John P. Hayes; Chris Sellathamby; Brian Moore; Steven Slupsky; Laurence Pujol

The traditionally wired interfaces of many electronic systems are in many applications being replaced by wireless interfaces. Testing of electronic systems (both integrated circuits and printed circuit boards) still requires physical electrical contact through probe needles and/or sockets. This paper addresses the state-of-the-art, options, and hurdles-still-to-take of contactless testing, which would resolve many test challenges due to shrinking size and pitch of pads and pins and inaccessibility of advanced assembly techniques as System-in-Package (SiP) and 3D stacked ICs.


international test conference | 2008

Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes

Brian Moore; Marc A. Mangrum; Chris Sellathamby; Md. Mahbub Reja; T. Weng; Brenda Bai; Edwin Walter Reid; Igor M. Filanovsky; Steven Slupsky

Non-contact methods for testing system-on-chip (SoC) and system in package (SIP) assemblies are presented. This method allows for high speed testing at the wafer level for SoCs as well as testing during and after assembly for panel or wafer level SIP technologies. Wafer testing at advanced nodes is carried out without damaging underlying metallurgy - an issue with current contact testing techniques. The technology utilizes non-contact GHz short-range transceivers to transfer test signals and results to and from SoC ICs. The wireless probes convert standard tester ATE logic levels to high frequency RF (GHz) transceiver signals and thus allow the use of standard test equipment. A reduced set of contact probes are used for test power only. A 45 nm fully CMOS compatible IC with wireless test transceivers is designed and fabricated. Enhancing the reliability and economics of IC manufacture by enabling non-contact testing of SoCs before and during packaging is a key benefit of this technology.


international midwest symposium on circuits and systems | 2009

A CMOS voltage reference using compensation of mobility and threshold voltage temperature effects

Igor M. Filanovsky; Brenda Bai; Brian Moore

A CMOS voltage reference using compensation of mobility and threshold voltage temperature effects is proposed. In this reference, the nested connection of two NMOS transistors supplies a voltage with positive temperature coefficient, and the diode-connected NMOS transistor supplies a voltage with negative temperature coefficient. These two circuits are connected in series via an operational amplifier, and the resulting voltage that appears in the output stage of this amplifier has low temperature coefficient. The calculations are verified by simulations of the reference designed in 0.13 µm CMOS technology. The simulated reference provides a voltage of about 490 mV with the variation of 1 mV in the temperature range 20 to 120°C. The reference is able to operate with sub-1V power supplies.


asia pacific conference on circuits and systems | 2008

Chip to chip communications for terabit transmission rates

Brian Moore; Chris Sellathamby; Steven Slupsky; Kris Iniewski

I/O data throughput remains a bottleneck in high-speed chip to chip data communication. This paper discusses the latest technical innovations in increasing the I/O bandwidth while reducing energy per transition. Both wireline techniques that include DSP processing and equalization, and wireless transmissions that include on-chip inductive and capacitive coupling are discussed and compared.


international symposium on circuits and systems | 2012

Contactless testing of on-chip oscillator operation

Igor M. Filanovsky; Brian Moore

The on-chip oscillator operation can be verified in a contactless way if the oscillator tank inductance is also used as a transmitting antenna. When the probing (receiver) antenna located on the test head is close to the oscillator, both antennas together may be considered as a transformer. The receiving antenna moving to and from the oscillator disturbs the oscillation frequency and amplitude, and these disturbances are registered by the measuring device connected to the receiving antenna. These disturbances, which are not occurring in ordinary oscillators with constant components, are evaluated using the equivalent circuit of thus formed transformer. The variation of frequency and the primary and secondary amplitudes as functions of distance between antennas are calculated. The results are experimentally verified with the oscillator realized in 0.13 μm CMOS technology.


Archive | 2009

Method and apparatus for interrogating electronic equipment components

Christopher V. Sellathamby; Steven Slupsky; Brian Moore


Archive | 2008

Ultra high speed signal transmission/reception

Steven Slupsky; Brian Moore; Christopher V. Sellathamby


Archive | 2008

Testing of electronic circuits using an active probe integrated circuit

Christopher V. Sellathamby; Steven Slupsky; Brian Moore


Archive | 2007

THIN FILM TRANSISTOR ARRAY HAVING TEST CIRCUITRY

Christopher V. Sellathamby; Steven Slupsky; Raymond George Decorby; Brian Moore

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Erik Jan Marinissen

Katholieke Universiteit Leuven

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