Vijay B. Rentala

A TDC-based test platform for dynamic circuit aging characterization

An on-chip 45nm test platform that directly monitors circuit performance degradation during dynamic operation is demonstrated. In contrast to traditional ring-oscillator (RO) based frequency measurements, it utilizes a Time-to-Digital Converter (TDC) with 2ps resolution to efficiently monitor circuit delay change on-the-fly. This new technique allows the capability of measuring signal edge degradation under various realistic circuit operating scenarios, such as asymmetric aging, dynamic voltage/frequency scaling, dynamic duty cycle factors, and temperature variations.

A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS

This paper presents a 160 GHz center frequency pulsed 65 nm CMOS transceiver for short range radar applications. Four phased array transceivers were implemented in a single chip with antennas implemented in a BGA package. The implemented transmitter is capable of producing pulses of 100 ps widths ( >20 GHz RF bandwidth) at a 160 GHz carrier frequency. The measured effective isotropic radiated power (EIRP) is 18.8 dBm for continuous wave outputs. The analog beam forming receiver achieves an overall gain of 42.5 dB, -14 dBm IP1dB, 7 GHz bandwidth, and a noise figure of 22.5 dB. The sliding window time-dilation baseband relaxes the output data rate and subsequent digital processing requirements. Fine grained duty cycling reduces power dissipation. The entire chip consumes 2.2 W from 1.2/1.4 V supplies in a 65 nm digital CMOS process.

A fully integrated 2×2 b/g and 1×2 a-band MIMO WLAN SoC in 45nm CMOS for multi-radio IC

A significant increase in Smartphones and tablets with embedded Wi-Fi demands a low-cost system solution. In this paper the RF core of an 802.11n 2×2 b/g band, 2×1 a-band MIMO WLAN SoC with die area of 3.83mm2 in 45nm CMOS is described. As shown in Fig. 19.1.1 the SoC has integrated Power Amplifier (PA) for both bands and T/R switch in b/g band, eliminating the need for an expensive external Front-End Module. The LO is synthesized by a two-step DLL-PLL architecture to meet the stringent phase-noise requirements.

A 1.16mW 69dB SNR (1.2MHz BW) continuous time £Δ ADC with immunity to clock jitter

A low-power jitter tolerant 2nd order active-passive continuous-time sigma-delta ADC in 65nm CMOS is presented. The use of just one active Gm-C integrator and a feed-forward path from the ADCs input to the Gms output helps reduce power consumption. A FIR filter in the outermost feedback path reduces clock jitter impact. For a −2dBFS input, the ADC clocked at 300MHz achieves a 69dB SNR (10KHz – 1.2MHz BW) while consuming 1.16mW from a 1.4V supply.

Low power ADC's for wireless communications

Recent advances in ADCs have enabled the development of low power receivers for wireless communication applications. In this paper we will discuss a specific class of ADCs, namely sigma delta ADCs. A brief overview of challenges in the design of these ADCs will be discussed along with the recent advances and techniques in overcoming these challenges. Two specific examples in the context of narrow and wide bandwidth systems will be discussed that demonstrate the viability of the recent techniques.

A 28mW WCDMA/GSM/GPRS/EDGE transformer-based receiver in 45nm CMOS

A transformer-based receiver designed in 45nm CMOS that meets WCDMA, GSM, GPRS, and EDGE system requirements is presented. The receiver requires no interstage SAW filters and consumes 20mA from 1.4V. The use of a transformer at the LNA output helps achieve high linearity by lowering the voltage swing while simultaneously providing current gain. The analog back end is implemented with two cascaded gain stages and a 2nd order ΣΔ ADC. The receiver has a gain of 60dB, noise figure of 3.0dB and an IIP2 of ≫+50dBm on both I+Q channels. The die area is 1.35mm2 for 4 bands.