Brian R. Koch

Hybrid Silicon Photonics for Optical Interconnects

In this paper, we review the hybrid silicon photonic integration platform and its use for optical links. In this platform, a III/V layer is bonded to a fully processed silicon-on-insulator wafer. By changing the bandgap of the III/V quantum wells (QW), low-threshold-current lasers, high-speed modulators, and photodetectors can be fabricated operating at wavelengths of 1.55 μm. With a QW intermixing technology, these components can be integrated with each other and a complete high-speed optical interconnect can be realized on-chip. The hybrid silicon bonding and process technology are fully compatible with CMOS-processed wafers because high-temperature steps and contamination are avoided. Full wafer bonding is possible, allowing for low-cost and large-volume device fabrication.

Mode-locked silicon evanescent lasers

We demonstrate electrically pumped lasers on silicon that produce pulses at repetition rates up to 40 GHz. The mode locked lasers generate 4 ps pulses with low jitter and extinction ratios above 18 dB, making them suitable for data and telecommunication transmitters and for clock generation and distribution. Results of both passive and hybrid mode locking are discussed. This type of device could enable new silicon based integrated technologies, such as optical time division multiplexing (OTDM), wavelength division multiplexing (WDM), and optical code division multiple access (OCDMA).

Device and Integration Technology for Silicon Photonic Transmitters

The device and integration technology for silicon photonic transmitters are reviewed in this paper. The hybrid silicon platform enables on-chip lasers to be fabricated with silicon photonic circuits and can be integrated in the CMOS back-end flow. Laser arrays from multiple die bonding and quantum well intermixing techniques are demonstrated to extend the spectral bandwidth from the laser array of the transmitter. Two modulator technologies, silicon modulators and hybrid silicon modulators, are also described.

A Distributed Bragg Reflector Silicon Evanescent Laser

We report a distributed Bragg reflector silicon evanescent laser operating continuous wave at 1596 nm. The lasing threshold and maximum output power are 65 mA and 11 mW, respectively. The device generates open eye-diagrams under direct modulation at data rates up to 4 Gb/s.

Demonstration of a High Speed 4-Channel Integrated Silicon Photonics WDM Link with Hybrid Silicon Lasers

The demonstration of a 4λ×10Gbps Silicon Photonics CWDM link integrating all optical components, electronics and packaging technologies required for system integration is reported. Further demonstration of the link operating at 50Gbps, 4λ×12.5Gbps, is also shown.

Single-Wavelength Silicon Evanescent Lasers

We review here recent work in the area of single wavelength silicon evanescent lasers that utilize distributed feedback, distributed Bragg reflector, and sampled grating distributed Bragg reflector laser topographies.

A racetrack mode-locked silicon evanescent laser

By utilizing a racetrack resonator topography, an on-chip mode locked silicon evanescent laser (ML-SEL) is realized that is independent of facet polishing. This enables integration with other devices on silicon and precise control of the ML-SELs repetition rate through lithographic definition of the cavity length. Both passive and hybrid mode-locking have been achieved with transform limited, 7 ps pulses emitted at a repetition rate of 30 GHz. Jitter and locking range are measured under hybrid mode locking with a minimum absolute jitter and maximum locking range of 364 fs, and 50 MHz, respectively.

Photonic Integration on the Hybrid Silicon Evanescent Device Platform

This paper reviews the recent progress of hybrid silicon evanescent devices. The hybrid silicon evanescent device structure consists of III-V epitaxial layers transferred to silicon waveguides through a low-temperature wafer bonding process to achieve optical gain, absorption, and modulation efficiently on a silicon photonics platform. The low-temperature wafer bonding process enables fusion of two different material systems without degradation of material quality and is scalable to wafer-level bonding. Lasers, amplifiers, photodetectors, and modulators have been demonstrated with this hybrid structure and integration of these individual components for improved optical functionality is also presented. This approach provides a unique way to build photonic active devices on silicon and should allow application of silicon photonic integrated circuits to optical telecommunication and optical interconnects.

Integrated Photonics for Low-Power Packet Networking

Communications interconnects and networks will continue to play a large role in contributing to the global carbon footprint, especially in data center and cloud-computing applications exponential growth in capacity. Key to maximizing the benefits of photonics technology is highly functional, lower power, and large-scale photonics integration. In this paper, we report on the latest advances in the photonic integration technologies used for asynchronous optical packet switching using an example photonic integrated switched optical router, the label switched optical router architecture. We report measurements of the power consumed by the photonic circuits in performing their intended function, the electronics required to bias the photonics, processing electronics, and required cooling technology. Data is presented to show that there is room (potentially greater than 10 ×) for improvement in the router packet-forwarding plane. The purpose of this exercise is not to provide a comparison of all-optical versus electronic routers, rather to present a data point on actual measurements of the power contributions for various photonic integration technologies of an all-optical packet router that has been demonstrated and conclude, where the technology can move to reduce power consumption for high-capacity packet routing systems.

Payload-envelope detection and label-detection integrated photonic circuit for asynchronous variable-length optical-packet switching with 40-gb/s RZ payloads and 10-gb/s NRZ labels

A photonic integrated circuit that performs 40-Gb/s payload-envelope detection (PED) and 10-Gb/s label detection for asynchronous variable-length optical-packet switching is demonstrated. The circuit consists of an InP photonic integrated device combined with electronic GaAs and InP devices on a carrier. Asynchronous variable-length optical packets with 40-Gb/s return-to-zero (RZ) payloads and 10-Gb/s non-RZ (NRZ) labels are processed by the circuit. The circuit outputs a PED electrical signal that represents the temporal location of the payload and a 10-Gb/s electrical signal representing the optical label. The optical label is detected error free. The PED signal has a rise/fall time of 3-ns and 150-ps jitter. The PED signal was also used to erase and rewrite the optical labels error free