Brian R. Wier
Georgia Institute of Technology
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Publication
Featured researches published by Brian R. Wier.
IEEE Electron Device Letters | 2014
Partha S. Chakraborty; Adilson S. Cardoso; Brian R. Wier; Anup P. Omprakash; John D. Cressler; Mehmet Kaynak; Bernd Tillack
We demonstrate record ac performance (0.8 THz) for a silicon-germanium heterojunction bipolar transistor (SiGe HBT) operating at cryogenic temperatures. An extracted peak fMAX of 798 GHz (peak fT of 479 GHz) at 4.3 K was measured for a device with a BVCEO of 1.67 V. This scaled SiGe HBT also exhibits excellent thermal properties, as required from an electro-thermal reliability perspective. Taken together, these results strongly suggest that at the limits of scaling, robust, and manufacturable SiGe HBTs designed for room temperature operation are likely to achieve THz speeds.
IEEE Transactions on Electron Devices | 2015
Michael A. Oakley; Uppili S. Raghunathan; Brian R. Wier; Partha S. Chakraborty; John D. Cressler
This paper presents the results of an investigation of the steady-state safe operating conditions for large-signal silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) circuits. By calculating capacitive currents within the intrinsic transistor, avalanche inducing currents through the transistor junctions are isolated and then compared with dc instability points established through simulation and measurement. In addition, calibrated technology computer-aided design simulations are used to provide further insight into the differences between RF and dc operation and stress conditions. The ability to swing the terminals of a SiGe HBT beyond the static I-V conditions coincident with catastrophic breakdown is explained. Furthermore, hot-carrier effects are also compared from multiple perspectives, with supporting data taken from fully realized X-band and C-band cascode driver amplifiers. This analysis provides microwave circuit designers with the framework necessary to better understand the full-voltage-swing potential of a given SiGe HBT technology and the resultant hot carrier damage under RF operation.
IEEE Transactions on Electron Devices | 2015
Uppili S. Raghunathan; Partha S. Chakraborty; Tikurete G. Bantu; Brian R. Wier; Hiroshi Yasuda; Philip Menz; John D. Cressler
This paper uses a physics-based TCAD degradation model to examine the accumulated stress damage of SiGe HBTs under pseudodynamic mixed-mode stress as a function of both electrical stress bias and temperature. The temperature dependence of mixed-mode stress damage is fully explored, beginning with impact-ionization calibration, and then by identifying and calibrating the dependence of scattering length and hydrogen diffusion parameters of the degradation model. After calibrating the model across electrical bias and temperature, the effectiveness and limitations of accumulated stress damage while varying electrical bias and while varying temperature are identified, and the implications of this aging model for circuit designers are discussed.
IEEE Transactions on Electron Devices | 2016
Brian R. Wier; Keith Green; Jonggook Kim; David T. Zweidinger; John D. Cressler
A physics-based silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) aging model for mixed-mode stress based on the lucky-electron model and reaction-diffusion theory is developed for integration with compact models. An effective aging parameter extraction method is described, and the aging model parameters are fit for a modern SiGe HBT platform. The aging model is implemented as a wrapper in the Cadence Spectre circuit simulator. Device-level aging simulations are shown to be well-matched to measured degradation data. The aging model is further used to explore the effects of aging on a simple current mirror circuit, showing a decrease in mirror ratio with degradation.
bipolar/bicmos circuits and technology meeting | 2013
Uppili S. Raghunathan; Partha S. Chakraborty; Brian R. Wier; John D. Cressler; Hiroshi Yasuda; Philipp Menz
We study the accumulated degradation of SiGe HBTs under time-dependent mixed-mode stress using a new physics-based TCAD degradation model that simulates hot carrier generation and propagation to oxide interfaces, resulting in trap formation. We calibrate the avalanche generation and also do a multipoint calibration of damage on the I-V output plane to accurately predict the accumulated stress damage for a single device over multiple bias points. Looking at the region of the output plane dominated by trap formation, we show that accumulation of traps can be path-independent as long as trap availability is not limiting. We demonstrate this with good correlation between simulation and measurement.
IEEE Transactions on Electron Devices | 2015
Brian R. Wier; Uppili S. Raghunathan; Partha S. Chakraborty; Hiroshi Yasuda; Philip Menz; John D. Cressler
We investigate and compare the hot-carrier degradation of SiGe HBTs under both traditional mixed-mode electrical stress conditions and high-current electrical stress conditions using measured stress data and an in-depth analysis of the underlying degradation mechanisms. While large electric fields are the driving force in mixed-mode hot-carrier degradation, the Auger recombination process is shown to be the hot-carrier source under high-current stress conditions. Auger hot-carrier degradation shows a positive temperature dependence, unlike mixed-mode degradation, due to the temperature dependence of Auger recombination and its energy distribution function. We also use calibrated TCAD simulations to explain an unexpected stress threshold behavior that occurs due to the formation of a potential well in the neutral base region, and to explore a field-compression effect at the collector/subcollector junction that contributes to trap formation at the shallow trench isolation oxide interface.
IEEE Transactions on Electron Devices | 2017
Uppili S. Raghunathan; Hanbin Ying; Brian R. Wier; Anup P. Omprakash; Partha S. Chakraborty; Tikurete G. Bantu; Hiroshi Yasuda; Philip Menz; John D. Cressler
This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability.
IEEE Electron Device Letters | 2017
Hanbin Ying; Brian R. Wier; Jason Dark; Nelson E. Lourenco; Luwei Ge; Anup P. Omprakash; Martin Mourigal; D. Davidović; John D. Cressler
We present the first measurement results of a highly scaled, 90-nm silicon-germanium heterojunction bipolar transistor (SiGe HBT) operating at cryogenic temperatures as low as 70 mK. The SiGe HBT exhibits a transistor-like behavior down to 70 mK, but below 40 K, the transconductance suggests the presence of nonequilibrium transport mechanisms. Despite the non-ideal base current at cryogenic temperatures, a dc current gain (β) > 1 is achieved for IC > 1 nA, suggesting that ultralow-power low-noise amplifiers should be viable. Exposure of the SiGe HBT to strong magnetic fields (±14 T) is also presented to help understand the nature of the non-ideal
radio frequency integrated circuits symposium | 2014
Michael A. Oakley; Brian R. Wier; Uppili S. Raghunathan; Partha S. Chakraborty; John D. Cressler
This paper investigates the RF reliability of SiGe HBT cascode driver amplifiers. By subtracting capacitive currents internal to the common-base device from its collector waveform, a more accurate depiction of electrical stress in the I-V plane is achieved, and from this revised load line, RF stress data is better correlated to DC stress data. This novel analysis technique provides a framework for designers to simulate the effects of RF stress using DC data from both TCAD models and measurements, allowing for optimized performance in high power and high frequency applications where reliability concerns often lead to under-utilization of the transistors capabilities.
bipolar/bicmos circuits and technology meeting | 2015
Zachary E. Fleetwood; Brian R. Wier; Uppili S. Raghunathan; Nelson E. Lourenco; Michael A. Oakley; Alvin J. Joseph; John D. Cressler
Profile optimization techniques are investigated for silicon-germanium heterojunction bipolar transistors (SiGe HBTs) intended for inverse-mode (IM) operation. IM device operation, also known as inverse active, involves electrically swapping the emitter and collector terminals and has been shown to improve the radiation tolerance of SiGe HBTs to single event transients (SETs). Multiple profile design variations are explored and trade-offs are analyzed with support of TCAD simulation. Modest design variations show marked improvement on IM performance while having minor impact on forward-mode (normal active) operation.