Ketan Shringarpure

Equivalent Circuit Model for Power Bus Design in Multi-Layer PCBs With Via Arrays

An equivalent circuit model for multilayer power planes with multiple via arrays is proposed. The complexity of the actual geometry is greatly reduced in the circuit model with the accuracy maintained. The model is corroborated by measurements.

Analytical expressions for transfer function of supply voltage fluctuation to jitter at a single-ended buffer

In this paper, the transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions. The expressions for the jitter transfer function is validated by comparison with HSPICE simulation, and applied to an example for statistical jitter estimation.

Characterization of PCB dielectric properties using two striplines on the same board

Signal integrity (SI) and power integrity (PI) modelling and design require accurate knowledge of dielectric properties of printed circuit board (PCB) laminate dielectrics. Dielectric properties of a laminate dielectric can be obtained from a set of the measured S-parameters on a PCB stripline with a specially designed through-reflect-line (TRL) calibration pattern. In this work, it is proposed to extract dielectric properties from the measurements of S-parameters on the two 50-Ohm stripline structures of the same length, but different widths of the trace, designed on the same layer of a PCB. The dielectric properties on these two lines should be identical. However, an application of the simplest “root-omega” technique to extract dielectric properties of the substrate would lead to the ambiguity in the extracted data. This is because the conductor surface roughness affects the measured S-parameters and is lumped in the extracted dielectric data. This problem of ambiguity in the dielectric properties extraction can be overcome using the approach analogous to the recently proposed method to separate dielectric and conductor losses on PCB lines with different widths and roughness profiles [1].

On finding the optimal number of decoupling capacitors by minimizing the equivalent inductance of the PCB PDN

PCB-PDN design remains a challenge with the reducing noise margins. One aspect of PDN design is finding the number of decoupling capacitors required for each power rail. As more capacitors are added, the mid frequency equivalent inductance in the impedance of the PCB-PDN converges to a minimum value for each placement pattern. This convergence is studied for different placement patterns to find the least number of capacitors required to satisfy a certain convergence criteria. A first principle method is used resonant cavity model for the analysis.

Analytical PDN voltage ripple calculation using simplified equivalent circuit model of PCB PDN

Printed circuit board (PCB) power distribution network (PDN) design performance depends on the peak voltage ripple caused by the integrated circuit (IC) switching currents. The input impedance seen by the IC looking into the PCB PDN can be calculated using a physics-based circuit model extracted from the cavity model approach. The input impedance is fitted to a simplified circuit model used to represent the PCB PDN. Using a switching current profile, the frequency domain noise voltage is found and transformed to the time domain ripple waveform which can then be used to evaluate the PDN design performance.

Formulation and Network Model Reduction for Analysis of the Power Distribution Network in a Production-Level Multilayered Printed Circuit Board

A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias.

Effect of narrow power fills on PCB PDN noise

The printed circuit board (PCB) power delivery network (PDN) performance has become critical with the reducing margins on power noise. This paper deals with a specific question about the size of the power area fill used to route the power current from the dc regulator to integrated circuit(IC), and also used for connecting to the decoupling capacitors. With increased PCB real estate costs, narrow power fills are required, which results in an increase in the connection inductance of decoupling capacitors. This paper uses a proven lumped circuit model extraction procedure, based on the first principle resonant cavity model, to demonstrate the effect of narrow and wide area fills used in typical PCB PDN designs. The frequency domain results thus obtained are used with typical IC current draw profiles to show the impact on the noise voltage developed at the IC. Some design guidelines and conclusions are drawn from these results.

Plane-pair PEEC models for PDN using sub-meshing

In this paper, we present an improved plane-pair model for power distribution system modeling using the partial element equivalent circuit approach. The modified nodal analysis with a sub-meshing strategy leads to an efficient and accurate circuit solution in both the frequency domain and time domain.

De-embedding techniques for transmission lines: An exploration, review, and proposal

In this paper, two transmission line based de-embedding techniques are reviewed for application in 3D IC measurements. In particular, full-wave models of extremely small stripline geometries are investigated. The advantages and drawbacks of each method are discussed in reference to simulation results, and a new hybrid method is proposed.

Effectiveness analysis of de-embedding method for typical TSV pairs in a silicon interposer

In this paper, a de-embedding method to extract the performance of a Through-Silicon-Via (TSV) pair is proposed, using a set of specially designed test patterns to remove the pads and connection trace. Considering in real implementations, wafer probe measurements are required to access the test structures, and any errors in the probe calibration affect the test pattern measurements, a micro-probe model is built in with the test. Short-Open-Load (SOL) calibration method is used with the simulation results to calibrate or correct to the tips of the micro-probe used in all test patterns. Calibrated responses for the test patterns consisting of probing pads, traces and TSV pair, thus are used with previously proposed de-embedding algorithm to characterize the TSV pair. The effectiveness and the robustness of the de-embedding method against probe calibration errors are tested with the full wave simulation results and analytical calculations.