Bryan Tracy

Measuring The Work Functions Of PVD TaN, TaSiN And TiSiN Films With A Schottky Diode CV Technique For Metal Gate CMOS Applications

The metal gate process becomes a promising candidate for sub-65nm CMOS, due to the elimination of polysilicon depletion effects, and the possibility of adjusting the CMOS threshold voltage without more threshold implants. Our goal is to process mteal films with tunable work functions, in order to meet the demand of sub-65nm metal gate CMOS. PVD TaN films are deposited with various processing conditions. Auger analysis shows that by changing the nitrogen flow rate and the plasma power, the nitrogen content in the TaN films can be adjusted. In order to accurately determine the work function of these TaN materials, we have developed a Schottky Diode CV technique (or Metal-Silicon CV, or MS-CV). This approach not only improves the accuracy of the metal work function measurement, compared with the traditional MOS-CV technique (which is affected by the thickness and quality of the oxide), but also simplifies the fabrication. With the MS-CVs, we have successfully measured the work functions of Ni and Co, and compared the data with published references. The work function of PVD TaN actually decreases with higher nitrogen content, according to the Auger data and the MS-CV measurement, ranging from 3.42 – 4.20 Volts. The MS-CV technique is shown to be independent to the size of the capacitors, and is little affected by the measurement frequency. By changing the frequency from 100KHz to 1MHz, the error in the work function is less than 50mV.

Self-aligned nickel, cobalt/tantalum nitride stacked-gate pMOSFETs fabricated with a low temperature process after metal electrode deposition

This letter reports the first replacement (Damascene) metal gate pMOSFETs fabricated with Ni/TaN, Co/TaN stacked electrode, where Ni or Co is in direct contact with the gate SiO/sub 2/, to adjust the electrode metal work function and TaN is used as the filling material for the gate electrode to avoid wet etching and CMP problems. The process is similar to the fabrication of traditional self-aligned polysilicon gate MOSFETs, except that in the back end (after the source/drain implants are activated) a few processing steps are added to replace the polysilicon with metal. Our data show that the Ni or Co/TaN gate electrode has the right work function for the pMOSFETs. The metal gate process can reduce the gate resistivity. Thermal stability of the stacked electrodes is studied and the result is reported in this paper. The damascene process flow bypasses high temperature steps (> 400/spl deg/C)critical for metal gate and hi k materials. This paper demonstrates that a low temperature anneal (300/spl deg/C) can improve the device performance. In this paper, the gate dielectrics is SiO/sub 2/.