Bum-Kyum Kim

A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization

A highly linear LNA is implemented in a 0.18 μm SOI CMOS process for 1 GHz SAW-less receiver applications. To achieve lower noise figure (NF) than conventional simultaneous noise and input matching methods, a capacitive loading based simultaneous noise and input matching technique reducing the NF degradation coming from a lossy gate inductor has been devised. In addition, in order to improve both the 1 dB gain compression point (CP1dB) and the third-order intercept point (IP3) without sacrificing NF, a large-signal transconductance linearization method adopting body-bias control and complementary-superposition is proposed. The proposed LNA shows a measured input-referred CP1dB of 3 dBm, 1 dB desensitization point (B1dB) of 0 dBm and IB (in-band)-IIP3 of 22 dBm with gain of 10.7 dB and NF of 1.3 dB at 1 GHz while driving a 50 Ω load impedance. It draws 20 mA with a buffer stage from a 2.5 V supply voltage.

A CMOS active feedback wideband single-to-differential LNA using inductive shunt-peaking for saw-less SDR receivers

A wideband active feedback single-to-differential (S-to-D) LNA composed of a S-to-D converter, a voltage combiner, and a negative feedback network is proposed. By feeding the single-ended output of the voltage combiner, which is used for combining the differential output of the S-to-D converter, to the input of the LNA through the feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. By using shunt-peaking of the source follower (SF) based active inductor, the proposed S-to-D LNA can achieve wider loop gain bandwidth with balun functionality. The 3-dB gain bandwidth of the proposed S-to-D LNA is above 5 GHz and the NF is below 4 dB from 100 MHz to 5 GHz. An average voltage gain of 18 dB and an ΠΡ3 of −5 dBm are obtained.

Hardware-efficient non-decimation RF sampling receiver front-end with reconfigurable FIR filtering

A hardware-efficient non-decimation RF sampling receiver front-end with reconfigurable finite impulse response (FIR) filtering is proposed for multi-band and multi-standard receivers. By adopting a moving average filtering with the charge accumulation, the hardware complexity of the non-decimation filter is only proportional to the number of taps. This makes the proposed non-decimation sampling filter suitable for high-frequency and high-selectivity sampling filters. With a sampling frequency of 1 GHz, a conversion gain of 20 dB and a cascaded NF of 7.5 dB are obtained at the output. The non-decimation FIR filter enhances out-of-band linearity by 10 dB, while suppressing aliasing by 55 dB. The chip is implemented using a 0.18-μm SOI CMOS technology and occupies 0.7 mm2.

A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

A stacked field-effect transistor (FET) linear cellular antenna switch adopting a transistor layout with odd-symmetrical drain-source metal wiring and an extremely low-power biasing strategy has been implemented in silicon-on-insulator CMOS technology. A multi-fingered switch-FET device with odd-symmetrical drain-source metal wiring is adopted herein to improve the insertion loss (IL) and isolation of the antenna switch by minimizing the product of the on-resistance and off-capacitance. To remove the spurious emission and digital switching noise problems from the antenna switch driver circuits, an extremely low-power biasing scheme driven by only positive bias voltage has been devised. The proposed antenna switch that employs the new biasing scheme shows almost the same power-handling capability and harmonic distortion as a conventional version based on a negative biasing scheme, while greatly reducing long start-up time and wasteful active current consumption in a stand-by mode of the conventional antenna switch driver circuits. The implemented single-pole four-throw antenna switch is perfectly capable of handling a high power signal up to +35 dBm with suitably low IL of less than 1 dB, and shows second- and third-order harmonic distortion of less than -45 dBm when a 1-GHz RF signal with a power of +35 dBm and a 2-GHz RF signal with a power of +33 dBm are applied. The proposed antenna switch consumes almost no static power.

Design methodology of tunable impedance matching circuit with SOI CMOS tunable capacitor array for RF FEM

For the tunable RF FEMs or Antennas, analysis on optimal design of tunable capacitors which consist of MIM capacitors and RF CMOS switches is performed in terms of quality factor, tuning ratio and harmonics. To handle up to +36dBm RF signal, the Stacked-FET and series Capacitor-Transistor-Capacitor (CTC) configuration applied Coupled-Bias(CB) are proposed, which in addition to being high-linearity can eliminate a negative voltage generator. Using the designed tunable capacitors, optimal tunable matching circuit is proposed.

A 1 GHz 1.3 dB NF +13 dBm output P1dB SOI CMOS low noise amplifier for SAW-less receivers

A complementary capacitive loaded LNA is implemented for 1 GHz application using a 0.18-μm SOI CMOS process. In order to improve both NF and linearity at the same time, the capacitive loading technique to achieve minimum NF and the complementary superposition with body-bias control to improve linearity are adopted. Owing to the capacitive loading technique, the required inductance of the gate inductor for minimum noise matching can be reduced compared to conventional inductive source-degenerated LNA. In case using on-chip gate inductor to implement fully integrated LNA, this greatly reduces the noise contribution of the gate inductor. The complementary superposition with body-bias control improves large signal linearity of gain compression (P1dB) as well as small signal linearity of third-order intercept point (IP3). The measurements demonstrate that the LNA, which is designed for 50 Ω system, has a power gain of 10.7 dB, a NF of 1.3 dB, an OIP3 of +29.1 dBm, and an output P1dB of +12.7 dBm at 1 GHz while drawing 20 mA from a 2.5 V supply voltage.

High-power tunable matching circuit using SOI-CMOS digitally programmable capacitor array for 4G mobile handsets

The design methodology for high power tunable matching circuit employing a SOICMOS based digitally programmable capacitor array is proposed. The power loss and matching performances of the antenna in combination with designed TMC network are greatly improved compared to the antennal only.

Equivalent circuit modeling of planar mobile phone intenna

Modeling of an inverted L antenna (ILA) on a small chassis is expressed in a form of an equivalent RLC circuit. The complete model of the ILA consists of three parts: antenna radiator (AR)s RLC resonator, chassis radiator (CR)s RLC resonators and an AR-CR coupler. AR and CRs RLC resonators are systematically defined. The interaction between the AR and the CR is analyzed in a straightforward manner by adjusting the turn ratio of a transformer in the AR-CR coupler.

Corrections to “A Highly Linear 1 GHz 1.3 dB NF CMOS Low-Noise Amplifier With Complementary Transconductance Linearization” [Jun 14 1286-1302]

In the above paper(B.-K. Kim, D. Im, J. Choi, and K. Lee, “A highly linear 1 GHz 1.3 dB NF CMOS low-noise amplifier with complementary transconductance linearization,” IEEE J. Solid-State Circuits, vol. 49, no. 6, pp. 1286–1302, Jun. 2014), a list of articles that should have been included as references are presented.

A low noise amplifier simultaneously achieving input impedance and minimum noise matching

A CMOS complementary capacitive loaded LNA with inductively source degeneration is implemented for 900MHz application using a 0.18-µm CMOS process. In order to achieve simultaneous input impedance and minimum noise matching, the capacitive loading technique is proposed. Owing to the capacitive loading technique, the noise figure (NF) of the proposed LNA can be perfectly close to NFmin while maintaining the source impedance matching by reducing the source degeneration inductor and gate inductor contrast to conventional cascode LNA with inductively source degeneration. The measurements demonstrate that the LNA has a power gain of 12 dB, a NF of 1 dB, an IIP3 of +7.7 dBm, and an input P1-dB of −5 dBm at 900 MHz while drawing 9 mA from a 1.8 V supply voltage.