Byong-Sun Ju

HIGH TEMPERATURE PLATINUM ETCHING USING TI MASK LAYER

Platinum is a strong candidate for an electrode material of the high dielectric capacitors in highly integrated dynamic random access memory devices. However, it is extremely difficult to etch the fine patterns of Pt due to an inherently low etch slope. This characteristic comes from the physical sputtering nature of the Pt etching process. This article reveals that the Pt etching profile depends on the change of the Ti mask layer caused by the increase of wafer temperature during etching. The Pt etching slope of 80° in 0.40 μm pitch was attained by heating the wafer substrate up to 220° with plasma-on. From the transmission electron microscopy analysis the Ti mask is considered to be deformed to TiOx layer in oxygen plasma at high wafer temperature, elevated either by high electrode temperature or plasma irradiation.

A study on the Pt electrode etching for 0.15 µm technologies

We have developed a high temperature Pt etching by using a titanium (Ti) mask layer in oxygen (O2)-containing plasma. The high temperature Pt etching technique has been employed to fabricate a stacked capacitor with a critical dimension (CD) of 0.15 µm. Due to reactive ion etching (RIE) lag, the Pt etch rate decreased drastically below the CD of 0.20 µm and, thus, the storage node electrode with the CD of 0.15 µm could not be fabricated. Accordingly, we have proposed novel techniques to surmount the above difficulties.

High-rate Ru electrode etching using O 2 /Cl 2 inductively coupled plasma

We have studied the characteristics of Ru etching using O2/Cl2 plasmas in an inductively coupled plasma (ICP) etcher. The changes of Ru etch rates and Ru electrode etching slopes by varying Cl2/(O2 + Cl2) gas flow ratio, total flow rate, source power, bias power, and pressure were investigated. A high Ru etch rate of > 1400 A/min with a high etching slope of > 85° was demonstrated using 0.15 µm critical dimension (CD) patterned wafers. The mechanism of high-rate Ru etching is studied.

Study of Ru etching using O2/Cl2 helicon plasmas

Abstract We have investigated the characteristics of ruthenium (Ru) etching using O 2 /Cl 2 helicon plasmas, resulting in the high Ru etch profile (>85°) and the optimal etch rate (>500 A min −1 ). We revealed that the chamber pressure greatly affects the Ru etch rate and Ru to mask etch selectivity. The dependence of Re etch rate on pressure was scrutinized for both patterned and non-patterned wafers.

Patterning of Ru electrode in O2/Cl2 gas using reactive ion etcher

Abstract We have studied the reactive ion etching of Ru electrode using O 2 /Cl 2 plasma. We have revealed that the Ru etch rate and thus the Ru to SiO 2 etch selectivity increase by increasing pressure, total gas flow rate, temperature and decreasing the HRF power and LRF power. The vertical Ru etching profile is attained.

Patterning of W/WN x /poly-Si gate electrode using Cl 2 /O 2 plasmas

The metal gate electrode with a tungsten (W)/tungsten nitride (WNx)/poly-Si structure has been successfully patterned by Cl2/O2 plasmas in a helicon etcher. The patterned metal gate electrode showed an almost vertical profile and no pitting of the gate oxide. The etch selectivity of W over polysilicon (poly-Si) increased with increasing source power, decreasing bias power, and increasing O2/(Cl2 + O2) gas flow ratio. We reveal that W etch rate enhances with increasing temperature.

Investigation on the Retention Reliability of Scaled

We investigate the retention reliability of a 51-nm-node 16-GB nand Flash cell transistor comprising SiO₂/Al_xO_y/SiO₂ inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse <i>V</i> _TH shift at 200°C 2-h bake and 53% improved <i>V</i> _TH shift after one week at 25°C, when compared to the case of ONO IPD.

\hbox{SiO}_{2}/\hbox{Al}_{x}\hbox{O}_{y}/\hbox{SiO}_{2}

The effects of chlorine plasma treatment on HfSiON gate dielectrics were investigated with respect to device performance and reliability characteristics. The chlorine plasma treatment was performed on atomic layer deposited HfSiON films to remove the residual carbon content. The optimal chlorine plasma treatment is shown to lower gate leakage current density without increasing equivalent oxide thickness of the gate stack. Secondary ion mass spectroscopy depth profiling showed that the carbon residue in HfSiON was reduced by the chlorine plasma treatment. It is demonstrated that an optimized chlorine plasma treatment improves the transistor Ion-Ioff characteristics and reduces negative-bias temperature instability.

Inter-Poly Dielectrics for nand Flash Cell Arrays

We have developed a concave-type Ru electrode capacitor to overcome the limitation of conventional stack-type capacitor in a small critical-dimension (CD) pattern. We have deposited a Ru layer on the concave-type structure made by patterning of SiO2 and subsequently we separated the adjacent nodes by an etch-back process with hydrogen silsesquioxane (HSQ) as a protecting layer. We have summarized the issues regarding the patterning in the reactive ion etching system for fabricating the concave-type capacitor.

Performance and reliability improvement of HfSiON gate dielectrics using chlorine plasma treatment

We have developed a concave-type Pt electrode capacitor to overcome the limitations of the conventional stack-type capacitor in a small critical dimension pattern. We deposited a Pt layer on the concave-type structure made by the patterning of SiO2 and subsequently separated the adjacent nodes by the etch-back process with a photoresist as a protecting layer. We summarize the issues regarding patterning in the reactive ion etching system for fabrication of a concave-type capacitor.