Byeong-Yun Nam

HIGH TEMPERATURE PLATINUM ETCHING USING TI MASK LAYER

Platinum is a strong candidate for an electrode material of the high dielectric capacitors in highly integrated dynamic random access memory devices. However, it is extremely difficult to etch the fine patterns of Pt due to an inherently low etch slope. This characteristic comes from the physical sputtering nature of the Pt etching process. This article reveals that the Pt etching profile depends on the change of the Ti mask layer caused by the increase of wafer temperature during etching. The Pt etching slope of 80° in 0.40 μm pitch was attained by heating the wafer substrate up to 220° with plasma-on. From the transmission electron microscopy analysis the Ti mask is considered to be deformed to TiOx layer in oxygen plasma at high wafer temperature, elevated either by high electrode temperature or plasma irradiation.

A robust alternative for the DRAM capacitor of 50 nm generation

As a new alternative for the DRAM capacitor of 50 nm generation, Ru/Insulator/TiN (RIT) capacitor with the lowest Toxeq of 0.85 nm has been successfully developed for the first time. TiO/sub 2//HfO/sub 2/ and Ta/sub 2/O/sub 5//HfO/sub 2/ double-layers were used as dielectric materials. After full integration into 512 Mbits DRAM device, the RIT capacitor showed good electrical properties and thermal stability up to 550/spl deg/C and its time-dependent-dielectric-breakdown behavior sufficiently satisfied 10-year lifetime within a DRAM operation voltage.

DRAM scaling-down to 0.1 /spl mu/m generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug

As DRAM downscaling approaches the 0.1 /spl mu/m generation, problems related to transistor short channel effects, storage capacitance, gap filling of high aspect ratio patterns, and leakage currents through each module must be solved. Among these, processing around the storage node self-aligned contact (SAC) is the most critical problem for integration of capacitor-on-bitline (COB) DRAM devices because it is one of the deepest contacts with high aspect ratio; and it reaches the cell transistor junction. However, few reports have addressed this issue, while others have been reported elsewhere (Song et al., 2000; Jeong et al., 2000; Won et al., 2000; Kim et al., 2000). In this paper, a novel process of bitline spacerless storage node SAC and Ru-Ta/sub 2/O/sub 5/-Ru (RIR) capacitor with TiN contact plug is studied for the integration of 0.1 /spl mu/m design-rule based DRAMs. It was found that the spacerless SAC process made downscaling to the 0.1 /spl mu/m design-rule possible and also that it has better electrical properties than the conventional SAC.