Byung-Ho Nam

EUV-patterning characterization using a 3D mask simulation and field EUV scanner

In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node. EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric characteristics of EUV scanner, shadowing effect produces CD variation versus field position[1][2]. Besides, it is well known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing effect and flare level are one of the important issues for EUV lithography. In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and space pattern is calculated.

Self-assembled dummy patterns for lithography process margin enhancement

Over the last couple of years, Design For Manufacturability (DFM) has progressed from concept to practice. What we thought then is actually applied to the design step to meet the high demand placed upon very high tech devices we make today. One of the DFM procedures that benefit the lithography process margin is generation of dummy patterns. Dummy pattern generated at design step enables stable yet high lithography process margin for many of the high technology device. But actual generation of the dummy pattern is very complex and risky for many of the layer used for memory devices. Dummy generation for simple pattern layers such as Poly or Isolation layer is not so difficult since pattern composed for these layers are usually 1 dimensional or very simple 2 dimensional patterns. But for interconnection layers that compose of complex 2 dimensional patterns, dummy pattern generation is very risky and requires lots of time and effort to safely place the dummy patterns. In this study, we propose simple self assembled dummy (SAD) generation algorithm to place dummy pattern for the complex 2 dimensional interconnection layers. This algorithm automatically self assembles dummy pattern based on the original design layout, therefore insuring the safety and simplicity of the generated dummy to the original design. Also we will evaluate SAD on interconnection layer using commercial Model Based Verification (MBV) tool to verify its applicability for both litho process margin and DFM perspective.

Binary and Attenuated PSM Mask evaluation for Sub 50nm Device Development Perspective

As the semiconductor industry continues progressing toward increasingly complex and unforgiving processes of device shrinkage and shorter duration of device development, many industry participants from photo-lithography are taking interest in material and structure of the photolithography mask. Due to shorter wavelength of the source laser and device technology ranging around the order of magnitude for the source laser wavelength (ArF), the difference in mask material and structure shows greater performance difference then larger technology node. Especially around 50nm and beyond, many industry followers are reporting better performance from different types of mask then previously used. In this study, we will analyze the effect of the photo lithography mask material for sub 50nm device, in development perspective. Two major types of mask will be evaluated on the scale of device development. Effects such as Mask Error Effect Factor (MEEF), Depth of Focus (DOF), Exposure Latitude (EL) and Critical Dimension Uniformity (CDU) will be analyzed for both binary and attenuated phase shifted mask under different process condition. Also, we will evaluate the comparison result for application on development of sub 45nm device.

Lithography process margin enhancement using illumination based assist pattern

The dawn of the Sub 100nm technology has brought many new exciting challenges for lithography process such as Immersion, OPC, asymmetry illumination, and so on. But, these new technology brought about new problems we face today due to shrinkage of the feature size. Some of the problems such as PR defect, ID bias and Mask Error Factor(MEF) are very important, but the most critical of all for lithography engineer is low process margin created by these technologies. In this study, we will be presenting the result of the Illumination based assist feature that enhances the lithography process margin for both Exposure Latitude (EL) and Depth Of Focus (DOF), while retaining safety of the scum generation by positioning the assist feature proportional to the illumination for 60nm device. Also, by automatically generating illumination based assist feature on the peripheral region of the mask, we will show that it levels the Critical Dimension (CD) uniformity for pattern of the same dimension located at both cell and peripheral region of the mask. Results will be tested on the mask feature size of 60nm and will be analyzed for both process margin and CD uniformity.

Highly accurate modeling by using 2-dimensional calibration data set for model-based OPC verification

As the k1 factor and minimum feature sizes decrease, the use of optical proximity correction (OPC) is increasing and is getting more complex. The complexity increases the possibility of correction errors like improper placement of edges in the OPC output data such that the printed results will deviate from target design. In this paper we will describe new modeling method by using 2-dimensional test structures for model based verification of post OPC data. Recently, most of the semiconductor companies implement a system for model based verification (MBV) for post OPC data into a manufacturing data flow. In case of model based verification, the most important thing is the accuracy of model which is used to detect the potential hot spot and critical errors like pinching-bridging errors and CD variation. For good model accuracy, process change has to be feedback to the model generation step by injecting real wafer information. Therefore, optimization process of 2-dimensional data set is needed. We proposed new modeling method by using optimization process of calibration data set which consists of 2-dimensional structures. Also, we present results of MBV and discuss about constraints and considerations of model based verification.

Gate CD Control for Memory Chip using Total Process Proximity Based Correction Method

In this study, we investigated mask errors, photo errors with attenuated phase shift mask and off-axis illumination, and etch errors in dry etch conditions. We propose that total process proximity correction (TPPC), a concept merging every process step error correction, is essential in a lithography process when minimum critical dimension (CD) is smaller than the wavelength of radiation. A correction rule table was experimentally obtained applying TPPC concept. Process capability of controlling gate CD in DRAM fabrication should be improved by this method.

Wafer scale error induced by bottom antireflective coating

Wafer-induced-shift caused by bottom anti-reflective coating (BARC) was observed during the misalignment compensation of stepper. This was represented as wafer scale component, that is, shot position dependence across the diameter of the wafer. Measurement error was quantified by comparison between pre- and post-etch pattern alignment data. Typical wafer scale value difference of 0.2ppm in 200mm diameter wafer was observed corresponding to maximum 20nm misalignment in the wafer edge. This is a detrimental value in critical mask step of current device manufacturing, and can be even more serious in next generation design rule adopting 300mm wafer, meaning maximum 30nm false measurement in the wafer edge. To reveal the cause of this phenomenon, the same sequential evaluation was performed without BARC application. No corresponding effect was detected supporting that BARC really caused such wafer-induced-shift. It was found that the wafer-induced-shift amount could be correlated with the size and shape of the alignment monitor pattern. We concluded that the wafer-induced-shift could be minimized by careful adoption of the alignment mark.

Lens aberration measurement and analysis using a novel pattern

Lens aberration of the exposure tool causes pattern deformation and position shift. As design rule shrinks, the ratio of printed feature size to applied wavelength for optical lithography is driven inexorably toward resolution limit. In this study, we devised an efficient method to evaluate lens aberration using multi-ring pattern on an attenuated phase-shift mask. Adoption of multi-ring pattern can cut down measurement time and improve measurement repeatability. These patterns are uniformly distributed through entire field in 7 by 7 manner. Lens aberration was evaluated by multi-ring pattern array under conventional or off-axis illumination with KrF stepper of NA 0.65. Multi-ring critical dimension (CD) data was discussed together with the issue of lens aberration such as coma, astigmatism, field curvature, etc. We can apply this new measurement technique to select better lens system efficiently. multi-ring, field size, pattern deformation

A method of utilizing AIMS to quantify lithographic performance of high transmittance mask

EUV (Extreme Ultraviolet) Lithography has been delayed caused by several technical problems such as EUV mask, source power and etc. So ArF immersion lithography has been continued with adopting new technology. Especially, the wafer lithography tends to increase rapidly NTD(Negative Tone Develop) process for overcoming high resolution such as small hole type patterns. For wafer NTD process, the pattern shape in mask has changed from hole pattern to dot pattern. Also the local CD uniformity of aerial image is getting more important. In this paper, we studied local CD uniformity with analyzing aerial images of high transmittance HT-PSM (attenuated phase-shift mask) and conventional 6% HT-PSM from AIMS (Aerial Image Measurement System) tool. Additionally, several cell sizes were analyzed to find an optimum target cell size which has good wafer performance and AIMS aerial image. And we analyzed NILS(Normalized Image Log Slope) factor which represent wafer photolithographic performance. Furthermore, we analyzed not only AIMS NILS simulation, but also wafer lithographic performance.

DFM application on dual tone sub 50nm device

As the semiconductor feature size continues to shrink, electrical resistance issue is becoming one of the industrys dreaded problems. In order to overcome such problem, many of the top semiconductor manufacturers have turned there interest to copper process. Widely known, copper process is the trench first damascene process which utilize dark tone mask instead of widely used clear tone mask. Due to unfamiliarity and under development of dark tone mask technology compared to clear tone mask, many have reported patterning defect issues using dark tone mask. Therefore, necessity of DFM[1] for design that meets both dark and clear tone is very large in development of copper process based device. In this study, we will propose a process friendly Design For Manufacturing (DFM) rule for dual tone mask. Proposed method guides the layout rule to give same performance from both dark tone and clear tone mask from same design layout. Our proposed method will be analyzed on photolithography process margin factors such as Depth Of Focus (DOF) and Exposure Latitude (EL) on sub 50nm Flash memory interconnection layer.