Hyoung-Soon Yune

Accuracy of diffused aerial image model for full-chip-level optical proximity correction

Recently, the miniaturization of the design rule of memory devices pushes the minimum feature sizes down to sub- wavelengths of the exposure tools. The design of a memory device comprises not only the dense patterns with critical small size in the cell region but also the random patterns in the peripheral region; the latter also need sub- wavelength lithography technology as well as the former. And the optical proximity correction (OPC) has been strongly required for the random patterns in the peripheral region where the same energy is exposed as in the cell region. Therefore, the high accuracy of simulation model used in the OPC is necessary for the full chip OPC tools. However traditional aerial image simulation has a limitation to the application due to its lack of accuracy because it does not take into account a resist process. We introduced novel lithography simulation model in 1998, which describes resist process by diffusion and chemically amplification function.

Novel process proximity correction by the pattern-to-pattern matching method with DBM

Recently, the dramatic acceleration in dimensional shrink of DRAM memory devices has been observed. For sub 60 nm memory device, we suggest the following method of optical proximity correction (OPC) to enhance the critical dimension uniformity (CDU). In order to enhance CD variation of each transistor, hundreds of thousand transistor CD data were used through design based metrology (DBM) system. In a traditional OPC modeling method, it is difficult to realize enhancement of CD variation on chip because of the limitation of OPC feedback data. Even though optical properties are surely understood from recent computational lithography models, there are so many abnormalities like mask effect, thermal effect from the wafer process, and etch bias variation of the etching process. Especially, etch bias is too complicate to predict since it is related to variations such as space among adjacent patterns, the density of neighboring patterns and so on. In this paper, process proximity correction (PPC) adopting the pattern to pattern matching method is used with huge amount of CD data from real wafer. This is the method which corrects CD bias with respect to each pattern by matching the same coordinates. New PPC method for enhancement of full chip CD variation is proposed which automatically corrects off-targeted feature by using full chip CD measurement data of DBM system. Thus, gate CDU of sub 60 nm node is reduced by using new PPC method. Analysis showed that our novel PPC method enhanced CD variation of full chip up to 20 percent.

Model-assisted template extraction SRAF application to contact holes patterns in high-end flash memory device fabrication

Sub-resolution assist feature (SRAF) insertion techniques have been effectively used for a long time now to increase process latitude in the lithography patterning process. Rule-based SRAF and model-based SRAF are complementary solutions, and each has its own benefits, depending on the objectives of applications and the criticality of the impact on manufacturing yield, efficiency, and productivity. Rule-based SRAF provides superior geometric output consistency and faster runtime performance, but the associated recipe development time can be of concern. Model-based SRAF provides better coverage for more complicated pattern structures in terms of shapes and sizes, with considerably less time required for recipe development, although consistency and performance may be impacted. In this paper, we introduce a new model-assisted template extraction (MATE) SRAF solution, which employs decision tree learning in a model-based solution to provide the benefits of both rule-based and model-based SRAF insertion approaches. The MATE solution is designed to automate the creation of rules/templates for SRAF insertion, and is based on the SRAF placement predicted by model-based solutions. The MATE SRAF recipe provides optimum lithographic quality in relation to various manufacturing aspects in a very short time, compared to traditional methods of rule optimization. Experiments were done using memory device pattern layouts to compare the MATE solution to existing model-based SRAF and pixelated SRAF approaches, based on lithographic process window quality, runtime performance, and geometric output consistency.

Process window variation comparison between NTD and PTD for various contact type

As technology node has been shrinking for bit growth, various technologies have been developed for high productivity. Nevertheless, lithography technology is close to its limit. In order to overcome these limits, EUV(Extreme Ultraviolet Lithography) and DSA(Directed Self-Assembly) are being developed, but there still exists problems for mass production. Currently, all lithography technology developments focus on solving the problems related to fine patterning and widening process window. One of the technologies is NTD(Negative Tone Development) which uses inverse development compared to PTD(Positive Tone Development). The exposed area is eliminated by positive developer in PTD, whereas the exposed area is remained in NTD. It is well known that NTD has better characteristics compared to PTD in terms of DOF(Depth of Focus) margin, MEEF(Mask Error Enhancement Factor), and LER(Line End Roughness) for both small contact holes and isolated spaces [1]. Contact hole patterning is especially more difficult than space patterning because of the lower image contrast and smaller process window [2]. Thus, we have focused on the trend of both NTD and PTD contact hole patterns in various environments. We have analyzed optical performance of both NTD and PTD according to size and pitch by SMO(Source Mask Optimization) software. Moreover, the simulation result of NTD process was compared with the NTD wafer level performance and the process window variation of NTD was characterized through both results. This result will be a good guideline to avoid DoF loss when using NTD process for contact layers with various contact types. In this paper, we studied the impact of different sources on various combinations of pattern sizes and pitches while estimating DOF trends aside from source and pattern types.

Study of various RET for process margin improvement in 3Xnm DRAM contact

As the DRAM node shrinks down to its natural limit, photo lithography is encountering many difficulties. 3Xnm DRAM node seems to be the limit for ArF Immersion. Until the arrival of EUV, double patterning (DPT) or spacer double patterning (SPT) seems like the next solution. But the problem with DPT or SPT is that both increases process step their by increasing the final costs of the device. So limiting the use of DPT or SPT is very important for device fabrication. For 3Xnm DRAM, storage node is one of the candidates to eliminate DPT or SPT process. But this method may cost lower process margin and degradation of pattern image. So, solution to these problems is very crucial. In this study, we will realize storage node (SN) pattern for 3Xnm DRAM node with improved process margin. First we will discuss selection of illumination for optimal condition second, correction of the mask will be introduced. We will also talk about the usage of various RET such as model based assist feature. Value such as DOF, EL and CDU (critical dimension uniformity) will be evaluated and analyzed.

Application of full-chip optical proximity correction for sub-60-nm memory device in polarized illumination

As the design rule shrinks to its natural limit, reduction in lithography process margin and high Critical Dimension (CD) error gives rise to use of many Resolution Enhancement Techniques (RET). Recently, one the popular RET method to solve the above problem is polarized illumination. It is used to enhance the reduced lithography process margin and enhance CD uniformity. Polarization lithography basically uses one sided polarized light source. Therefore process margin increases for smaller design rule patterns. In this paper, we will present the results for polarized illumination based Optical proximity Correction (OPC) for sub-60nm memory device. First, models for polarization based and un-polarization based method will be compared for its model accuracy. Second, the process margin improvement for polarized and un-polarized illumination will be compared and analyzed for poly layer of sub-60nm memory device. Finally, method for further enhancing CD error within 5% for polarized OPC model will be discussed.

Highly accurate hybrid-OPC method for sub-60nm memory device

Recently, as the design rule shrinks so does the CD tolerance. Therefore, the importance of simulation and OPC accuracy is increasing. In the past, when pattern size was large, rule-based OPC was acceptable but as the design rule shrinks accuracy of OPC turned to model-based OPC and almost all device uses this method. Model-based OPC is based on parameter fitting it has Model-Residual-Error (MRE). Due to this error the accuracy of the model has limitations. Usually variable-threshold or vector model is applied to the model in order to cut down the MRE. But still, size of the MRE is too large compared to CD tolerance. Currently, further development of model-based OPC resulted in creation of both model and rule-based OPC. This is called Hybrid OPC method. Hybrid-OPC method is based on model OPC but MRE can be lowered using rule bias to retarget the design data. But this method makes it difficult to retarget the design data in that rule biasing result is hard to predict after the model-based OPC operation. In this paper, we propose New Hybrid OPC method that feeds back the MRE calibrated data set to model-based OPC method. By using this method, better OPC model can be made. We will be presenting the result after the method has been applied on sub-60nm device and the capability of this method.

Double-exposure strategy using OPC and simulation and the performance on wafer with sub-0.10-μm design rule in ArF lithography

As the pattern size becomes smaller, double or multi exposure is required unless the epochal solutions for overcoming the limits of present lithography system do appear or are discovered. ArF DET (double exposure technology) strategy based on manual OPC with in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method to extend the limitation of current lithography. HOST requires no additional procedures and separate layout optimizations of each region in terms of OPC are enough. Furthermore, it is possible to change illumination condition of each region and the overlap between two regions with ease. The results from the simulation are pattern size and profile of each condition according to the defous and misregistration. 0.63 NA ArF Scanner and Clariant resist is used for wafer process. The resist was coated on Clariant organic BARC using 0.24 um thickness. Dipole illumination for cell region and annular illumination for peripheral region are used. Cell region contains 0.20 um pitch duty pattern and peripheral region 0.24 um pitch duty pattern. The boundary of two regions is investigated in view of validity of stitching itself. The layout of reticles used as the cell and peripheral region are optimized by OPC, respectively and then, additional OPC was treated to the boundary, i.e., stitching area to compensate the cross term of the boundary caused by separate and independent optimization with OPC in the cell and the peripheral regime. The final patterns were acquired by defining the cell at first and the peripheral region secondly with different defocus and registration in respect to the cell. The actual data on wafer are presented according to defocus and one regions overlay offset relatively to the other region. And the outstanding matching between simulation results and in-line data are shown. Lithography process window for stable patterning is thoroughly investigated in view of depth of focus, energy latitude, registration between two stitched regions and stitching itself in the boundary. It is found from the experiment that total DOF of DE (double exposure) is 0.5 um and the total EL of DE is 10.0% in this paper. At present, it is very difficult to ensure stable process margin for the sub-0.10 um patterning. But there is a promising technology called stitching with special optimization. In addition, this technology will be nominated as an eternal candidate process whenever our lithography is in the adversity at the limits of his days.

The double exposure strategy using OPC and simulation and the performance on wafer with sub-0.10 /spl mu/m design rule in ArF lithography

Lately, photolithography is seen as the bottleneck to sub-0.1 /spl mu/m patterning. Namely, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as in the cell region into the resolution limit of exposure tools. Although it is common to use single exposure for lithographic layer formation, an ArF double exposure technique (DET) strategy, based on manual OPC and an in-house simulation tool, HOST (Hynix OPC simulation tool), is suggested as a possible exposure method for overcoming the limit and its results on wafer are shown. The in-house simulation tool used in this paper can predict the wafer pattern and process margin of a lithographic layer and shows good validity in the ArF process.

Application of full-chip level optical proximity correction to memory device with sub-0.10-μm design rule and ArF lithography

Recently, the miniaturization of the design rule pushes the pattern sizes in the peripheral region as well as cell region to the resolution limit of exposure tools. Therefore it is necessary to apply optical proximity correction (OPC) not only to the patterns in cell region but also to those in peripheral region. It is impossible to apply manual OPC method in peripheral region. Because the peripheral region is composed of random patterns with large data volume, and it takes too long execution time with manual OPC. For random pattern OPC in peripheral region, automatic OPC tool is required. Now for the automatic OPC tool, model-based and rule-based methods are developed for the commercial use. In this paper, the effectively applicable process is discussed using model-based method in automatic OPC at the sub-0.10 micrometer design rule in ArF lithography. For the application of automatic OPC tool at the design rule of sub-0.10 micrometer and ArF process in memory devices the following problem should be cleared. In small size of design rule, we should consider not only pattern fidelity but also process margin such as depth of focus (DOF) and exposure latitude (EL) at the cell OPC. But automatic OPC tool is insufficient to be applied for cell region OPC, because it considers not process margin but pattern fidelity and it has low accuracy using much approximation model to reduce layout correction time. To solve this problem, we suggest a full chip OPC process using both automatic OPC tool and the manual OPC method using the novel lithography simulation model (Diffused Aerial Image Model, DAIM). DAIM is available to predict wafer pattern and process margin of cell, its accuracy is verified in ArF process as in KrF process. We could see small standard deviation error between experiment and DAIM in ArF process using various line or space patterns, which is about 9 nm at binary intensity mask (BIM). So the manual OPC with DAIM resulted in the wide process margin and good pattern fidelity overcoming the limitation of automatic OPC tool. However it is necessary to correlate energy level of DAIM for cell region OPC with that of the model in the automatic OPC tool for peripheral region OPC, because cell and peripheral region are exposed with the same exposure dose in stepper or scanner. In case of ArF process, we could see the small difference of energy level and standard deviation error, which is about 1.4%, 2 nm at BIM and 6.3%, 3 nm at half-tone phase shift mask (PSM), between DAIM and automatic OPC tool. As the result of using DAIM and automatic OPC tool simultaneously at full chip OPC, we could see improved results from cell to peripheral region at the sub-0.10 micrometer design rule in ArF lithography.