Cheol-Kyun Kim

Evaluation of shadowing and flare effect for EUV tool

One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography. In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirks disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.

Comprehensive EUV lithography model

As EUV lithography nears pilot-line stage, photolithography modeling becomes increasingly important in order for engineers to build viable, production-worthy processes. In this paper, we present a comprehensive, calibrated lithography model that includes optical effects such as mask shadowing and flare, combined with a stochastic resist model that can predict effects such as line-edge roughness. The model was calibrated to CD versus pitch data with varying levels of flare, as well as dense lines with varying degrees of mask shadowing. We then use this model to investigate several issues critical to EUV. First, we investigate EUV photoresist technology: the impact of photoelectron-PAG exposure kinetics on photospeed, and then we examine the trade-off between LWR and photospeed by changing quencher loading in the photoresist model. Second, we compare the predicted process windows for dense lines as flare and lens aberrations are reduced from the levels in the current alpha tools to the levels expected in the beta tools. The observed interactions between optical improvements and resist LWR indicate that a comprehensive model is required to provide a realistic evaluation of a lithography process.

Evaluation of Inverse Lithography Technology for 55nm-node memory device

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

DFM flow by using combination between design-based metrology system and model-based verification at sub-50nm memory device

As the minimum transistor length is getting smaller, the variation and uniformity of transistor length seriously effect device performance. So, the importance of optical proximity effects correction (OPC) and resolution enhancement technology (RET) cannot be overemphasized. However, OPC process is regarded by some as a necessary evil in device performance. In fact, every group which includes process and design, are interested in whole chip CD variation trend and CD uniformity, which represent real wafer. Recently, design based metrology systems are capable of detecting difference between data base to wafer SEM image. Design based metrology systems are able to extract information of whole chip CD variation. According to the results, OPC abnormality was identified and design feedback items are also disclosed. The other approaches are accomplished on EDA companies, like model based OPC verifications. Model based verification will be done for full chip area by using well-calibrated model. The object of model based verification is the prediction of potential weak point on wafer and fast feed back to OPC and design before reticle fabrication. In order to achieve robust design and sufficient device margin, appropriate combination between design based metrology system and model based verification tools is very important. Therefore, we evaluated design based metrology system and matched model based verification system for optimum combination between two systems. In our study, huge amount of data from wafer results are classified and analyzed by statistical method and classified by OPC feedback and design feedback items. Additionally, novel DFM flow would be proposed by using combination of design based metrology and model based verification tools.

Comparison of simulation and wafer results for shadowing and flare effect on EUV alpha demo tool

In this study, in order to accurately predict the shadowing and flare effect of EUVL, we compared and analyzed the wafer and simulation result of the shadowing and flare effect of the EUV alpha demo tool at IMEC. Flare distribution of the EUV Alpha Demo tool was measured and was used in simulation tool to simulate several test case wafer result. Also, shadowing effect of the in-house created mask was measured and compared with simulation result to match the predictability of the simulation tool. Shadowing test comparison of wafer to simulation showed that simulation with resist model showing better overall fitness to actual wafer result. Both aerial and resist model simulation result was within 2.33nm to wafer result. Measured wafer CD to simulation CD comparison for flare showed that average error RMS of 3 test cases was 0.52, 2.05 and 3.47 nm for each test case respectively. In order to have higher accuracy for flare simulation, larger diameter size for flare profile is necessary. Also from shadow test, resist model better fit the wafer trend than using only the aerial image for simulating shadowing effect. EUV tool showed very promising result for sub 30nm DRAM critical layer printing ability and with proper flare and shadowing correction, reasonable result is expected for sub 30 and beyond critical layers of DRAM using EUV lithography. Further work will be done to compensate flare and shadowing effect of EUV.

Scanner matching using pupil intensity control between scanners in 30nm DRAM device

Scanner mismatch has become one of the critical issues in high volume memory production. There are several components that contribute to the scanner CD mismatch. One of the major components is illumination pupil difference between scanners. Because of acceleration of dimensional shrinking in memory devices, the CD mismatch became more critical in electrical performance and process window. In this work, we demonstrated computational lithography model based scanner matching for sub 3x nm memory devices. We used ASML XT:1900Gi as a reference scanner and ASML NXT:1950i as the to-be-matched scanner. Wafer metrology data and scanner specific parameters are used to build a computational model, and determine the optimal settings by model simulation to minimize the CD difference between scanners. Nano Geometry Research (NGR) was used as a wafer CD metrology tool for both model calibration and matching result verification. The extracted pupil parameters from measured source map from both before and after matching are inspected and analyzed. Simulated and measured process window changes by applying the matching sub-recipe are also evaluated.

Analysis of the impact of pupil shape variation by pupil fit modeling

As K1 factor for mass-production of memory devices has been decreased to almost its theoretical limit, the process window of lithography is getting much smaller and the production yield has become more sensitive to even small variations of the process in lithography. So it is necessary to control the process variations more tightly than ever. In mass-production, it is very hard to extend the production capacity if the tool-to-tool variation of scanners and/or scanner stability through time is not minimized. One of the most critical sources of variation is the illumination pupil. So it is critical to qualify the shape of pupils in scanners to control tool-to-tool variations. Traditionally, the pupil shape has been analyzed by using classical pupil parameters to define pupil shape, but these basic parameters, sometimes, cannot distinguish the tool-to-tool variations. It has been found that the pupil shape can be changed by illumination misalignment or damages in optics and theses changes can have a great effect on critical dimension (CD), pattern profile or OPC accuracy. These imaging effects are not captured by the basic pupil parameters. The correlation between CD and pupil parameters will become even more difficult with the introduction of more complex (freeform) illumination pupils. In this paper, illumination pupils were analyzed using a more sophisticated parametric pupil description (Pupil Fit Model, PFM). And the impact of pupil shape variations on CD for critical features is investigated. The tool-to-tool mismatching in gate layer of 4X memory device was demonstrated for an example. Also, we interpreted which parameter is most sensitive to CD for different applications. It was found that the more sophisticated parametric pupil description is much better compared to the traditional way of pupil control. However, our examples also show that the tool-to-tool pupil variation and pupil variation through time of a scanner can not be adequately monitored by pupil parameters only, The best pupil control strategy is a combination of pupil parameters and simulated CD using measured illumination pupils or modeled pupils.

Novel process proximity correction by the pattern-to-pattern matching method with DBM

Recently, the dramatic acceleration in dimensional shrink of DRAM memory devices has been observed. For sub 60 nm memory device, we suggest the following method of optical proximity correction (OPC) to enhance the critical dimension uniformity (CDU). In order to enhance CD variation of each transistor, hundreds of thousand transistor CD data were used through design based metrology (DBM) system. In a traditional OPC modeling method, it is difficult to realize enhancement of CD variation on chip because of the limitation of OPC feedback data. Even though optical properties are surely understood from recent computational lithography models, there are so many abnormalities like mask effect, thermal effect from the wafer process, and etch bias variation of the etching process. Especially, etch bias is too complicate to predict since it is related to variations such as space among adjacent patterns, the density of neighboring patterns and so on. In this paper, process proximity correction (PPC) adopting the pattern to pattern matching method is used with huge amount of CD data from real wafer. This is the method which corrects CD bias with respect to each pattern by matching the same coordinates. New PPC method for enhancement of full chip CD variation is proposed which automatically corrects off-targeted feature by using full chip CD measurement data of DBM system. Thus, gate CDU of sub 60 nm node is reduced by using new PPC method. Analysis showed that our novel PPC method enhanced CD variation of full chip up to 20 percent.

Study of model-assisted rule base SRAF for random contact

In this paper, we will evaluate model assisted rule base SRAF. Model assisted rule base SRAF combines the advantage of both model based SRAF and rule base SRAF to ensure high process margin without the mask making difficulty with stable wafer output. Model will assist in generating a common rule for rule based SRAF. Method to extract the rule from the models will first be discussed. Model assisted rule based SRAF will be applied to 3Xnm DRAM contact. Evaluation and analysis of the simulated and actual wafer result will be discussed. Our wafer result showed that by applying Model assisted rule based SRAF showed nearly equal performance to models based SRAF with clearly better stability and mask fabrication feasibility.

Highly accurate modeling by using 2-dimensional calibration data set for model-based OPC verification

As the k1 factor and minimum feature sizes decrease, the use of optical proximity correction (OPC) is increasing and is getting more complex. The complexity increases the possibility of correction errors like improper placement of edges in the OPC output data such that the printed results will deviate from target design. In this paper we will describe new modeling method by using 2-dimensional test structures for model based verification of post OPC data. Recently, most of the semiconductor companies implement a system for model based verification (MBV) for post OPC data into a manufacturing data flow. In case of model based verification, the most important thing is the accuracy of model which is used to detect the potential hot spot and critical errors like pinching-bridging errors and CD variation. For good model accuracy, process change has to be feedback to the model generation step by injecting real wafer information. Therefore, optimization process of 2-dimensional data set is needed. We proposed new modeling method by using optimization process of calibration data set which consists of 2-dimensional structures. Also, we present results of MBV and discuss about constraints and considerations of model based verification.