Byung-Seok Lee

Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool

Double patterning technique using spacer which can avoid CD (Critical Dimension) uniformity problem mainly caused by overlay issue is one of the methods that could be applied to apply to manufacturing of memory devices. Though double exposure and etch technology (DEET) has comparative advantage in the number of process steps, it is required to dramatically improve overlay performance of current exposure tools for the realization of manufacturing. In this study, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning. Negative type-double patterning technique using spacer consists of subsequent steps such as formation of poly line, spacer on sidewall of poly line, SOG gap fill into space between poly lines, SOG etch back, removal of spacer, and finally hard mask etch. We have used amorphous carbon as a spacer material to easily remove spacer from poly lines and adopted SOG material to easily fill in space between poly lines. When negative type-double patterning technique using spacer is applied to NAND flash memory device, we can expect that k1 factor of about 0.14~0.20 could be accomplished successfully.

Double patterning of contact array with carbon polymer

The spacer patterning technique (SPT) is well known as one of the methods expanding the resolution limit and mainly useful for patterning line & space of memory device. Although contact array could be achieved by both spacer patterning technique and double exposure & etch technique (DEET) 1, the former would be preferable to the latter by the issues of overlay burden and resolution limit of isolated contact. The process procedure for contact array is similar to that for line & space which involves the 1st mask exposure, etch, carbon polymer deposition, the 2nd mask exposure and etch step sequentially. With SPT, it would be possible to realize contact array of 30nm half pitch including 30nm isolated contact as well as line & space of 30nm half pitch.

A middle-1X nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies

A middle-1x nm design rule multi-level NAND flash memory cell (M1X-NAND) has been successfully developed for the first time. 1) QSPT (Quad Spacer Patterning Technology) of ArF immersion lithography is used for patterning mid-1x nm rule wordline (WL). In order to achieve high performance and reliability, several integration technologies are adopted, such as 2) advanced WL air-gap process, 3) floating gate slimming process, and 4) optimized junction formation scheme. And also, by using 5) new N±1 WL Vpass scheme during programming, charge loss and program speed are greatly improved. As a result, mid-1x nm design rule NAND flash memories has been successfully realized.

Effects of CH 2 F 2 Addition on a High Aspect Ratio Contact Hole Etching in a C 4 F 6 / O 2 / Ar Plasma

An SiO 2 contact hole with a diameter of 0.17 μm and an aspect ratio of 15 was etched in C 4 F 6 /O 2 /Ar and C 4 F 6 /O 2 /Ar/CH 2 F 2 plasmas, and the effects of CH 2 F 2 gas on the etch profiles and the etch selectivity to photoresist were investigated. The addition of CH 2 F 2 gas enhanced the production of fluorocarbon films by reactive C-F species, resulting in more fluorocarbon films deposited on the photoresist layer and the sidewalls of the contact hole compared to the CH 2 F 2 gas being absent. This finally led to drastic improvements in the critical dimension loss and the etched contact profiles. The etch selectivity to photoresist was also enhanced in the presence of CH 2 F 2 gas due to hydrogen atoms as well as reactive C-F species. X-ray photoelectron spectroscopy analyses showed that the fluorocarbon films produced in the C 4 F 6 /O 2 /Ar/CΗ 2 F 2 plasma were more carbon-rich compared to those in the C 4 F 6 /O 2 /Ar plasma.

Highly reliable M1X MLC NAND flash memory cell with novel active air-gap and p+ poly process integration technologies

Our Middle-1X nm MLC NAND (M1X) flash cell is intensively characterized with respect to reliability and manufacturability. For the first time, the novel active air-gap technology is applied to alleviate the drop of channel boosting potential of program inhibition mode, BL-BL interference is reduced to our 2y nm node level by this novel integration technology. Furthermore, it also relaxes the effect of process variation like EFH (Effective Field oxide Height) on cell Vt distribution. Better endurance and retention characteristics can be obtained by p+ doped poly gate. By optimization of active air-gap profile and poly doping level, M1X nm MLC NAND flash memory has been successfully implemented with superior manufacturability and acceptable reliability.

Air-Gap Application and Simulation Results for Low Capacitance in 60nm NAND Flash Memory

In IMD study Rs reduction and better uniformity as well as lower capacitance were achieved in 60 nm 2 Giga Bit NAND flash memory. It alos fabricated 70 % air-gap of gate and calculated interference reduction in 45 nm device when it was applied throughout simulation. It is sure that we should apply this air-gap process to future device in order to meet device property of cell Vt shift and capacitance.

A study of an acid-induced defect on chemically amplified photoresist applied to sub-30nm NAND flash memory

Recently, we found a peculiar acid induced defect on chemically amplified photo resist applied to sub- 30nm NAND Flash Memory. This defect is like a hole-pattern with about 1um diameter, and induced by diffusion of acid which makes photoresist soluble in developer, even though photoresist is not exposed with KrF. With some experiment results, we found out that HCl gas, by-product of high temperature oxide which is contained inside voids between two gate lines diffuses into photoresist through high temperature oxide from voids, makes photoresist soluble in developer, and eventually creates the hole-type defect on photoresist. To prevent this defect, we can suggest some methods which are substitution of KrF photoresist into I-line photoresist, modification of oxide deposition recipe to suppress by-product, and applying of non-CAR (Chemically Amplification Resist) type KrF photoresist not sensitive to acid.

Improvement of Poly Profile in Sub 30 nm Device By Damage Engineering and Tilted Implantation Method

Conventionally, P31 out‐gassing of floating gate by succeeding thermal processes happens in NAND FLASH that use floating gate structure, and this P31 out gassing causes degradation of PDR and cell characteristics in sub‐30 nm device. Usually, there is a method to keep PDR of in‐situ doped poly‐Si by increasing the concentration of P31, but this method also causes cell characteristics degradation by trap charge of tunnel oxide.So, we used another method of ion implantation to control P31 out‐gassing concentration of floating gate by declining effective channel length. If we use methods of low energy and zero tilt implantation, P31 Trap by dopant channeling occurs in tunnel oxide. So, we evaluated methods of low energy and tilted implantation. But in this case, there were poly loss and bending, due to the physical collision damage of implantation.Therefore, we evaluated the effects of tilt change, direction and temperature control of ion implantation to minimize poly loss of floating gate.

Process step reduction at negative tone spacer patterning technique using developer soluble bottom ARC

While spacer is essential to separate the second lines from the first lines at negative tone spacer patterning technique, Spacer brings side effects such as increase in process step as well as CD budget induced by spacer. To eliminate these side effects, we have chosen the combination of photo resist as the first lines and developer soluble bottom ARC as the second lines at negative tone spacer patterning technique. This process scheme consists of only two mask steps; one is critical mask for the first lines in cell and peripheral cell, and another is non-critical mask for recess of the second lines in cell area and removal of the second lines in peripheral area. By the diffusion of acid from photo resist into developer soluble bottom ARC, developer soluble bottom ARC adjacent to photo resist of the first line is transformed into the substance, which can be easily removed by developer dispensed after the second mask exposure. With the adoption of developer soluble bottom ARC, we can expect to make progress in cost reduction at negative tone spacer patterning technique.

Failure Analysis of an Anomalous Subthreshold Current in Nano-Scale NAND Flash Memory

As the design rule of NAND-type memory decreases down to sub 100 nm tech regime, one of important problems is the control of the parasitic transistor phenomenon. The parasitic transistor which causes subthreshold kink at high substrate bias is a common phenomenon for STI (shallow trench isolation) technology, especially for isolation whose pitch needs to be shrunk. To resolve the degradation of device performance by the subthreshold hump, many process solution has been reported (Park, 2000). Furthermore, in the fabrication of nano-scale silicon device, accurate 2D failure analysis is one of the important fields to be solved. In this paper, we present the numerical simulation study of STI implant process factor to suppress anomalous hump effect and investigate feasibility of the application of scanning capacitance microscopy (SCM) and chemical staining method in 2D failure analysis of 70nm NAND flash device