Wooyung Jung

Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool

Double patterning technique using spacer which can avoid CD (Critical Dimension) uniformity problem mainly caused by overlay issue is one of the methods that could be applied to apply to manufacturing of memory devices. Though double exposure and etch technology (DEET) has comparative advantage in the number of process steps, it is required to dramatically improve overlay performance of current exposure tools for the realization of manufacturing. In this study, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning. Negative type-double patterning technique using spacer consists of subsequent steps such as formation of poly line, spacer on sidewall of poly line, SOG gap fill into space between poly lines, SOG etch back, removal of spacer, and finally hard mask etch. We have used amorphous carbon as a spacer material to easily remove spacer from poly lines and adopted SOG material to easily fill in space between poly lines. When negative type-double patterning technique using spacer is applied to NAND flash memory device, we can expect that k1 factor of about 0.14~0.20 could be accomplished successfully.

Double patterning of contact array with carbon polymer

The spacer patterning technique (SPT) is well known as one of the methods expanding the resolution limit and mainly useful for patterning line & space of memory device. Although contact array could be achieved by both spacer patterning technique and double exposure & etch technique (DEET) 1, the former would be preferable to the latter by the issues of overlay burden and resolution limit of isolated contact. The process procedure for contact array is similar to that for line & space which involves the 1st mask exposure, etch, carbon polymer deposition, the 2nd mask exposure and etch step sequentially. With SPT, it would be possible to realize contact array of 30nm half pitch including 30nm isolated contact as well as line & space of 30nm half pitch.

NIL defect performance toward high volume mass production

A low cost alternative lithographic technology is desired to meet with the decreasing feature size of semiconductor devices. Nanoimprint lithography (NIL) is one of the candidates for alternative lithographic technologies. NIL has advantages such as good resolution, critical dimension (CD) uniformity and smaller line edge roughness (LER). 4 On the other hand, NIL involves some risks. Defectivity is the most critical issue in NIL. The progress in the defect reduction on templates shows great improvement recently. In other words, the defect reduction of the NIIL process is a key to apply NIL to mass production. In this paper, we describe the evaluation results of the defect performance of NIL using an up-to-date tool, Canon FPA-1100 NZ2, and discuss the future potential of NIL in terms of defectivity. The impact of various kinds defects, such as the non-filling defect, plug defect, line collapse, and defects on replica templates are discussed. We found that non-fill defects under the resist pattern cause line collapse. It is important to prevent line collapse. From these analyses based on actual NIL defect data on long-run stability, we will show the way to reduce defects and the possibility of NIL in device high volume mass production. For the past one year, we have been are collaborating with SK Hynix to bring this promising technology into mainstream manufacturing. This work is the result of this collaboration.

Overlay improvement in nanoimprint lithography for 1×-nm patterning

Nanoimprint lithography (NIL) is becoming a promising technique for fine-patterning with a lower cost than other lithography techniques. High overlay accuracy is one of the issues in NIL. Using die-by-die alignment with moire fringe detection, an NIL alignment measurement accuracy below 1 nm and an overlay accuracy below 5 nm have been reported. On the other hand, the requirement for overlay in 2020 is estimated to be 3–4 nm for dynamic random access memory, flash and logic devices. In order to make the overlay accuracy requirement qualify from the semiconductor industry, a lot of technology enhancements, such as the improvement of overlay control accuracy for NIL-tools, image placement accuracy improvement for NIL templates, mix and match technique of NIL, and other lithography tools such as immersion exposure ones, are needed. In this paper, the authors describe the evaluation of the NIL overlay performance using up-to-date NIL tools, and discuss the potentials of NIL overlay in the future. Alignment ac...

Scatterometry-based process control for nanoimprint lithography

In principal, the critical dimension (CD) of Nanoimprint lithography (NIL) pattern is determined by the CD of the template pattern. Unless one template is changed to another, NIL does not have a knob for direct control of the CD, such as the exposure dose and focus in optical lithography. Alternatively, the CD would be controlled by adjusting the thickness of the residual layer underneath the NIL pattern and controlling the etching process to transfer the pattern to a substrate. Controlling the residual layer thickness (RLT) can change the etching bias, resulting in the control of the CD of etched pattern. RLT is controllable by the resist dispense condition of the inkjet. For CD control, the metrology of RLT and feedback of the results to the dispense condition are extremely important. Scatterometry is the most promising metrology for the task because it is nondestructive 3D metrology with high throughput. In this paper, we discuss how to control CD in the NIL process and propose a process control flow based on scatterometry.

Study of nanoimprint lithography (NIL) for HVM of memory devices

A low cost alternative lithographic technology is desired to meet the decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the candidates for alternative lithographic technologies.[1][2][3] NIL has such advantages as good resolution, critical dimension (CD) uniformity and low line edge roughness (LER). On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the HVM, it is necessary to overcome these three challenges simultaneously.[4]-[12] In our previous study, we have reported a dramatic improvement in NIL process defectivity on a pilot line tool, FPA-1100 NZ2. We have described that the NIL process for 2x nm half pitch is getting closer to the target of HVM.[12] In this study, we report the recent evaluation of the NIL process performance to judge the applicability of NIL to memory device fabrications. In detail, the CD uniformity and LER are found to be less than 2nm. The overlay accuracy of the test device is less than 7nm. A defectivity level of below 1pcs./cm2 has been achieved at a throughput of 15 wafers per hour.

Process control technology for nanoimprint lithography

Nanoimprint lithography (NIL) is regarded as one of the candidates for next generation lithography toward singlenanometer manufacturing. Among the wide variety of imprint methods, Jet and Flash Imprint Lithography (J-FIL) process is the most suitable for IC manufacturing for which high productivity and high precision is required. Unlike spin-coating-based NIL process J-FIL process has some capabilities to solve the issue by controlling local resist volume based on pattern design of the patterned mask (template). In order to improve NIL process, in this paper we focus on understanding the occurrence of non-filling defects during resist filling into the template features, and propose the new optimization concept of drop amount and drop arrangement for fast filling and defect reduction.

Material development for high-throughput nanoimprint lithography

Nanoimprint lithography (NIL) is a candidate of alternative lithographic technology for memory devices. We are developing NIL technology and challenging critical issues such as defectivity, overlay, and throughput . NIL material is a key factor to support the robust patterning process. Especially, resist material can play an important role in addressing the issue of the total throughput performance. The aim of this research is to clarify key factors of resist property which can reduce resist filling time and template separation time . The liquid resist is filled in the relief patterns on a quartz template surface and subsequently cured under UV radiation. The filling time is a bottleneck of NILthroughput. We have clarified that the air trapping in the liquid resist is critical. Based on theoretical study, we have identified key factors of NIL-resist property. These results have provided a deeper insight into resist material for high throughput NIL.

Improvement of nano-imprint lithography performance for device fabrication

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.[1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.[4]-[10] In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.[8]Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.

The opportunity and challenge of spin coat based nanoimprint lithography

Since multi patterning with spacer was introduced in NAND flash memory1, multi patterning with spacer has been a promising solution to overcome the resolution limit. However, the increase in process cost of multi patterning with spacer must be a serious burden to device manufacturers as half pitch of patterns gets smaller.2, 3 Even though Nano Imprint Lithography (NIL) has been considered as one of strong candidates to avoid cost issue of multi patterning with spacer, there are still negative viewpoints; template damage induced from particles between template and wafer, overlay degradation induced from shear force between template and wafer, and throughput loss induced from dispensing and spreading resist droplet. Jet and Flash Imprint Lithography (J-FIL4, 5, 6) has contributed to throughput improvement, but still has these above problems. J-FIL consists of 5 steps; dispense of resist droplets on wafer, imprinting template on wafer, filling the gap between template and wafer with resist, UV curing, and separation of template from wafer. If dispensing resist droplets by inkjet is replaced with coating resist at spin coater, additional progress in NIL can be achieved. Template damage from particle can be suppressed by thick resist which is spin-coated at spin coater and covers most of particles on wafer, shear force between template and wafer can be minimized with thick resist, and finally additional throughput enhancement can be achieved by skipping dispense of resist droplets on wafer. On the other hand, spin-coat-based NIL has side effect such as pattern collapse which comes from high separation energy of resist. It is expected that pattern collapse can be improved by the development of resist with low separation energy.