C. Anghel

Self-heating characterization and extraction method for thermal resistance and capacitance in high voltage MOSFETs

This work reports on the self-heating effect (SHE) characterization of HV DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analysed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method of device thermal resistance and capacitance exploits analytical modelling and dedicated extraction plots using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are assumed and extracted in saturation region as quasi-independent functions of the device bias (injected power) at a given external temperature. We originally report on the temperature dependence of the HV device thermal resistance that is shown to be a linear function of external temperature (in our device, R/sub TH/ could increase by almost 100% over 100/spl deg/C). SPICE simulations with the extracted thermal R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.This letter reports on the self-heating effect (SHE) characterization of high-voltage (HV) DMOSFETs and the accurate extraction of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/) needed for advanced device and IC simulation. A simple pulsed-gate experiment is proposed and the influence of its parameters (pulse duration and duty factor) are analyzed. It is demonstrated that in our 100 V DMOSFET, SHE is cancelled by using pulses with duration less that 2 /spl mu/s and duty factor lower that 1:100. The new extraction method exploits analytical modeling and dedicated extraction plots for thermal resistance and capacitance using the measurements of output characteristics at various applied pulses and the gradual reduction of SHE with pulse duration and duty factor. Both R/sub TH/ and C/sub TH/ are extracted in saturation region considering their dependence on SHE and external temperature. In DMOSFETs, the thermal resistance is shown to be a significant linear function of the device temperature (in our device, R/sub TH/ could increase by more than 100% over 100/spl deg/C). The thermal capacitance appears to decrease with the injected power and shows a plateau at high V/sub D/. SPICE simulations with the extracted thermal network R/sub TH/-C/sub TH/ circuit are finally used to fully validate the proposed method.

Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET

A detailed investigation of the drift resistance evolution with the gate and drain biases in Lateral DMOS architectures is reported. The extractions are performed using the concept of intrinsic drain voltage, V/sub K/, applied to both simulated and measured data. Some new special test structures (MESDRIFT) have been designed and fabricated in order to investigate the DMOS bias-dependent drift resistance and experimentally confirm 2D numerical simulations. Some of the physical origins, associated with drift resistance dependence on gate and drain bias, are discussed. A simple yet efficient DMOS macro-modeling strategy is reported. It consists of combining a low-voltage BSIM model module with a bias-dependent series resistance described by a quasi-empirical mathematical expression. All LDMOS operation regimes (including quasi-saturation) are captured by the proposed expression and data measured on MESDRIFT is used to calibrate the BSIM and drift parameters. The methodology does not dependent on the drift architecture and can be applied to any similar asymmetric HV MOS devices.

Analysis and Modeling of Lateral Non-Uniform Doping in High-Voltage MOSFETs

This paper reports on the impact and modeling of lateral doping gradient present in the intrinsic MOS channel of high voltage MOSFETs e.g. VDMOS and LDMOS. It is shown that the conventional MOSFET models using uniform lateral doping can never correctly model the capacitance behavior of these devices. A new charge-based analytical compact model for lateral non-uniformly doped MOSFET is reported. The model is validated on the measured characteristics of VDMOS and LDMOS transistors. The model shows good results in DC and, most importantly in AC regime, especially in simulating the peaks in CGD, CGS and CGG capacitances. This new model improves the accuracy of high voltage MOS models, especially output characteristics and during transient response (i.e. amplitude and position of peaks as well as slope of capacitances)

New method for temperature-dependent thermal resistance and capacitance accurate extraction in high-voltage DMOS transistors

This work reports on the self-heating-effect (SHE) characterization of high-voltage (HV) DMOSFETs and a simple yet accurate extraction methodology of the equivalent thermal impedance of the device (thermal resistance, R/sub TH/, and capacitance, C/sub TH/). Systematic pulsed-gate experiments are used to study the influence of pulse duration and duty factor on device SHE and optimal extraction conditions. It is found that in 100 V DMOSFETs, the SHE is cancelled by using pulses with duration shorter than 2 /spl mu/s and duty factors lower than 1:100. The new extraction method uses dedicated extraction plots exploiting the gradual canceling of SHE with pulse duration and a new analytical modeling including the temperature dependence of RTH, is validated. For the first time, we report on the temperature dependence of RTH, from 25/spl deg/C up to 150/spl deg/C, in both saturation and quasi-saturation regions of DMOS, which is shown to be a quasi-linear yet significant function of the device internal temperature. Moreover, another new result is a power low-dependent thermal capacitance, as suggested by our experiments. Finally, SPICE simulations are used to validate the proposed method, and, demonstrate that a thermal-dependent thermal resistance model is highly critical for accurate advanced simulation of HV DMOS ICs.

A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor

A modeling strategy for high voltage VDMOS transistors based on the intrinsic drain voltage and the use of EKV MOSFET model as a core for the intrinsic MOS channel is presented. The proposed charge based model correctly reproduces the special effects of high voltage devices like the quasi saturation, impact ionization and self heating. The accuracy of the model is better than 5% for DC I-V and g-V characteristics. We also report the accurate simulation of the intrinsic drain voltage, VK, which represents the basis of the AC model. The unique peaks on Cgs and Cgd characteristics peculiar to high voltage devices are accurately simulated by this charge based model. It is demonstrated that this model provides excellent trade-off between speed, convergence and accuracy, being suitable for circuit simulation in any operation regime of HV MOSFETs including all special effects of these devices

New method for threshold voltage extraction of high-voltage MOSFETs based on gate-to-drain capacitance measurement

This letter reports on the extraction of the threshold voltage of laterally diffused MOS transistors. A clear analysis of the device physics is performed, highlighting the correlation between the change of the electron charge distribution along the channel and the device capacitance variations when the gate voltage is swept. Using numerical simulations, it is shown that the peak of the gate-to-drain capacitance is related to the transition of the surface from weak to moderate inversion in the intrinsic MOS transistor at the location of the maximum doping concentration, which corresponds to the threshold voltage of the device according to the MOS theory. Comparison between conventional I/sub D///spl radic/g/sub m/ extraction and the new proposed capacitance peak method is performed on both technology computer-aided design simulations and measurements in order to confirm the new experimental technique and related theory.

A Highly Scalable High Voltage MOSFET Model

The authors propose a new highly scalable general high voltage MOSFET model for circuit simulation. A new general drift resistance model for the drift part is proposed while intrinsic MOS channel is modeled using low voltage EKV MOS model. The proposed general model is highly scalable for major physical and electrical parameters. It is shown that the model performs excellently over a wide range of DC bias condition along with the scalability against transistor width; drift length, number of fingers and temperature. The model shows good behavior for all capacitances which are unique for these devices showing peaks and shift of peaks with bias variation. The model is validated on the measured characteristics of LDMOS and VDMOS devices

Universal Test Structure and Characterization Method for Bias-Dependent Drift Series Resistance of HV MOSFETs

A simple, fast and accurate characterisation method dedicated to the evaluation of bias-dependent drift resistance of the HV MOS transistors is presented. The procedure relies on a novel test design structure that gives direct information about the impact of the drift zone on the overall HV MOSFET characteristics. Intrinsic (MOS channel) and extrinsic (including drift region) characteristics, obtained by adapted measurements, are used for parameter extraction and physical effects identification. For the first time the variation of the drift resistance from room temperature up to 150°C is extracted. Very good performance when combining a BSIM3V3 low voltage model with a drift resistance quasiempirical model is reported.

A physical analysis of HV MOSFET capacitance behaviour

This work reports on the physical effects that appear on the AC characteristics of the high voltage LDMOS transistors. A qualitative explanation for the variation of the charges inside the device is proposed. TCAD simulations are used to sustain the presented theory. Finally, the specific peaks that appear on C/sub GS/ and C/sub GD/ characteristics function of the gate voltage are explained.

Hot carrier degradation of lateral DMOS transistor capacitance and reliability issues

This paper reports on an experimental evaluation of the hot-carrier impact on capacitances of high voltage DMOS transistors and their correlation with the degradation of DC characteristics. Two stress conditions were selected: (i) stress-A: at maximum drain voltage (near breakdown) and a gate voltage providing maximum body-current, I/sub Bmax/, and; (ii) stress-B: at maximum drain and gate voltages, which are the most relevant for device reliability. The proposed investigations experimentally distinguish among drift-region degradation, for stress-A, and gate oxide degradation near the source-end, for stress-B. In the case of stress-B, while traditional DC evaluation of stress impact suggests a significant shift in the DC parameters, the DMOS AC characteristics appear considerably altered. This suggests the importance of the systematic experimental evaluation of the impact of hot-carrier degradation of AC characteristics and its correlation with DC degradation in order to explain the degradation mechanisms.