C.C. Liao

On-The-Fly Interface Trap Measurement and Its Impact on the Understanding of NBTI Mechanism for p-MOSFETs with SiON Gate Dielectric

For the first time, we developed an on-the-fly method OFIT to measure the interface trap density N_IT without recovery during measurement. The OFIT produces the most reliable experimental data of the interface trap generation dynamics under stress and therefore provides a solid ground to check various modeling work. The slope n of tⁿ time evolution of DeltaN_IT under stress is temperature dependent, supporting dispersive Hydrogen transport in the oxide. Comparing OFIT data with the data measured by ultra-fast pulsed V_th measurement, we successfully decompose the NBTI DeltaV_TH into interface trap component DeltaV_TH ^IT and oxide charge component DeltaV_TH ^OX quantitatively for the p-MOSFETs with SiON gate dielectric.

A Modified Charge-Pumping Method for the Characterization of Interface-Trap Generation in MOSFETs

A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence ( ~ t n) of interface-trap generation is observed. The index n is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics.

Comprehensive studies of BTI effects in CMOSFETs with SiON by new measurement techniques

In this work, we combine our recently developed recovery free on-the-fly interface traps measurement (OFIT) and fast-pulsed-measurement (FPM) to conduct a comprehensive study of BTI degradations for both n- and p-MOSFETs with SiON gate dielectric. The results provide the most reliable data for the understanding and modeling of BTI degradation and also provide new insights to re-access the impact of BTI in logic and analog circuits and SRAM applications.

Anomalous Negative Bias Temperature Instability Degradation Induced by Source/Drain Bias in Nanoscale PMOS Devices

The effect of source/drain (S/D) bias on the negative bias temperature instability (NBTI) of pMOSFETs is studied. The anomalously enhanced NBTI under S/D bias conditions is observed, which cannot be explained by the conventional reaction-diffusion model. A new mechanism based on the enhanced interfacial dissociation of equivSi-H bonds induced by the energetic holes (the hole energy Eh is higher than the reaction activation energy Ea of equivSi-H bond dissociation) is proposed to address the observed degradation behaviors. Monte Carlo simulations are used to identify the validity of the new mechanism.

Scalable Modeling of MOSFET Source and Drain Resistances for MS/RF Circuit Simulation

Large-width and short-length MOS transistors with multi-finger layouts are necessary for the mixed-signal and RF IC designs to achieve optimum gain and noise performances. As the total width (i.e., the product of the finger width and the number of fingers Nfg) increases, the parasitic source and drain resistances due to the contact and diffusion regions becomes comparable in magnitude to the MOSFET intrinsic channel resistances under many (bias and layout) scenarios and, hence, require accurate and scalable SPICE modeling. This paper presents a model for multi-finger MOSFET source /drain contacts and diffusion parasitic resistances, and a simple parameter extraction methodology to take into account the unwanted parasitic impacts from the wiring and measurement equipment; both can be readily applied to BSIM3v3 and BSIM4. Excellent accuracy and scalability have been achieved in comparison with measurement

Models of Source/Drain Bias on Negative Bias Temperature Instability

This paper discusses the influence of source/drain (S/D) bias on negative bias temperature instability (NBTI) in pMOS devices. It is found that with the S/D bias increase, the NBTI degradation is initially reduced, but it increases with higher S/D bias. Two models are presented to explain the underlying mechanisms. One is the graded hydrogen density model, which dominates at the low S/D bias; and the other is the energetic hole model, which successfully explains the high threshold voltage (Vth) shift at high S/D bias

A New Failure Mechanism of Gate-grounded MOSFET ESD Device in 9Onm Technology

A new triggering phenomenon was observed on gate-grounded nMOS (ggnMOS) ESD device in 90nm technology. The trigger voltage has been measured at the value as low as 6V. However, the low triggering voltage does not result in high ESD performance as conventional theory suggested. The experimental data and simulation results have shown that this is due to the dislocation of the largest electric field from drain/junction region to the edge of LDD/pocket region. Therefore heating in the smaller LDD/pocket junction causes the early burn out. It is clarified that lower trigger voltage does not always mean to higher ESD endurance.

Factors for negative bias temperature instability improvement in deep sub-micron CMOS technology

Negative bias temperature instability (NBTI) in PMOS has emerged as one of the critical reliability concerns in deep sub-micron devices. A comprehensive study has performed to improve the device NBTI performance by process optimization. It is found that the most effective ways to reduce the NBTI degradation are to control the nitrogen concentration and profile in the nitrided gate oxide, to implement LDD and source/drain implantation by BF2 instead of by B, and to employ a lower annealing temperature and a more diluted H2/N2 mixture. It is seen that the nitrogen incorporation mainly results in more oxide traps. By optimizing the decoupled plasma nitridation (DPN) process, the nitrogen peak/profile should be controlled away from the oxide/Si interface, thus reducing the oxide trap and improving NBTI performance. Incorporation of fluorine species during source/drain implantation can reduce both interface traps and oxide traps.

Studies of NBTI in pMOSFETs with thermal and plasma nitrided SiON gate oxides by OFIT and FPM methods

NBTI in pMOSFETs with plasma (PNO) and thermal (TNO) nitrided SiON gate oxides are re-investigated using our newly developed on-the-fly interface trap (OFIT) and fast pulse I–V measurement (FPM) methods. The threshold voltage shift ΔVTH is quantitatively decomposed into interface trap and oxide charge components. It is found that the interface trap generation under stress follows the power law with the same power index n and its temperature dependence, indicating the same interface degradation mechanism for both PNO and TNO devices. The NBTI degradation in TNO devices is larger than those in PNO devices, particularly the larger component of oxide charge. The result is explained by the different N profile of TNO from that of PNO devices, as supported by the first principle calculation.

Issues and controversies in NBTI degradation and recovery mechanisms for p-MOSFETs with SiON gate dielectrics

Some issues and controversies in NBTI degradation and recovery mechanisms for p-MOSFETs with SiON gate dielectrics are summarized. The resolutions of these issues from our point of view are illustrated.