Waisum Wong

A 0.4-V Low Noise Amplifier Using Forward Body Bias Technology for 5 GHz Application

A fully integrated low noise amplifier (LNA) suitable for ultra low voltage and ultra low power applications is proposed and demonstrated in 0.13 mum CMOS technology. In order to meet the requirement of ultra low voltage applications, a two-stage common-source configuration is employed. By using forward-body-biased metal oxide semiconductor field effect transistors, the proposed LNA can operate at 0.4 V supply voltage, successfully demonstrating the application potential of dynamic threshold voltage technology in the radio frequency region. The experimental results show that the proposed LNA has a 10.3 dB power gain and a 5.3 dB noise figure, while consuming only 1.03 mW dc power with an ultra low supply voltage of 0.4 V.

On-The-Fly Interface Trap Measurement and Its Impact on the Understanding of NBTI Mechanism for p-MOSFETs with SiON Gate Dielectric

For the first time, we developed an on-the-fly method OFIT to measure the interface trap density N_IT without recovery during measurement. The OFIT produces the most reliable experimental data of the interface trap generation dynamics under stress and therefore provides a solid ground to check various modeling work. The slope n of tⁿ time evolution of DeltaN_IT under stress is temperature dependent, supporting dispersive Hydrogen transport in the oxide. Comparing OFIT data with the data measured by ultra-fast pulsed V_th measurement, we successfully decompose the NBTI DeltaV_TH into interface trap component DeltaV_TH ^IT and oxide charge component DeltaV_TH ^OX quantitatively for the p-MOSFETs with SiON gate dielectric.

A new approach to extract the threshold voltage of MOSFETs

A new method is presented to extract the threshold voltage of MOSFETs. It is developed based on an integral function which is insensitive to the drain and source series resistances of the MOSFETs. The method is tested in the environments of circuit simulator (SPICE), device simulation (MEDICI), and measurements.

A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

In this paper, the major physical effects caused by gate oxide traps in MOSFETs have been integrated for the first time by a proposed unified approach in realistic manners based on industry-standard EDA tools, aiming at practical trap-aware device/circuit co-design. The recently-found AC or transient effects of traps and the interplays with manufacturing process variations are included, with demonstrations on two representatives (RO and SRAM) under realistic digital circuit operations. The proposed approach and the results are helpful for robust and resilient device/circuit co-design in future nano-CMOS technology.

A Wideband Predictive “Double- ” Equivalent-Circuit Model for On-Chip Spiral Inductors

A new wideband predictive ldquodouble-pirdquo equivalent-circuit model for on-chip spiral inductors is presented, in which the model parameters are analytically calculated with layout and process parameters. In the model, five major parasitic effects, including skin effect, proximity effect, distributed effect, substrate capacitive loss, and inductive loss, are implemented together. Considering skin effect and proximity effect simultaneously, a new equation of high-frequency resistance is proposed, and accordingly, two coupled transformer loops are developed, respectively, to calculate the network parameters of skin effect, proximity effect, and substrate inductive coupling effect independently. In order to analytically calculate substrate capacitive loss in multiturn inductors, a quasi-linear relationship between capacitive coupling effect and proximity effect is established. A series of inductors with different geometries are fabricated in two standard RFCMOS processes to verify the model. Excellent agreements have been obtained between the measured data and the proposed model within a wide frequency range. Since a clear relationship between circuit components and fabrication parameters is defined, it can precisely predict the performance of the inductors and become more flexible in RFIC design.

A Novel RF LDMOS Fabricated With Standard Foundry Technology

In this letter, a novel LDMOS structure is proposed and experimentally demonstrated with standard foundry CMOS technology. The device features both an inserted oxide layer in the drift region as the ldquoelectric field line absorberrdquo and a high-doped region introduced for action of the RESURF-like structure. The RESURF-Dielectric-region-Inserted LDMOS device with breakdown voltage of about 15 V and peak cutoff frequency of 18 GHz is obtained. The proposed device also exhibits good reliability behavior under high-voltage stressing. The new device is very promising for integrated power amplifier circuit design with the standard CMOS process.

A Modified Charge-Pumping Method for the Characterization of Interface-Trap Generation in MOSFETs

A novel recovery-free interface-trap measurement method is presented in detail. This method is the modification of the conventional charge pumping (CP) by extending the pulse low level to the stress-bias and minimizing the pulse high-level duty cycle to suppress the recovery effect. The method is applied to study the negative-bias temperature instability in p-MOSFETs. As compared with the conventional CP, a much larger interface-trap generation under stress is observed by the new method. A power law time dependence ( ~ t n) of interface-trap generation is observed. The index n is less than that derived from conventional CP and increases with temperature, demonstrating a dispersive process involved in the trap generation dynamics.

New insights into the design for end-of-life variability of NBTI in scaled high-κ/metal-gate Technology for the nano-reliability era

In this paper, a new methodology for the assessment of end-of-life variability of NBTI is proposed for the first time. By introducing the concept of characteristic failure probability, the uncertainty in the predicted 10-year VDD is addressed. Based on this, variability resulted from NBTI degradation at end of life under specific VDD is extensively studied with a novel characterization technique. With the further circuit level analysis based on this new methodology, the timing margin can be relaxed. The new methodology has also been extended to FinFET in this work. The wide applicability of this methodology is helpful to future reliability/variability-aware circuit design in nano-CMOS technology.

A Wideband Predictive "Double-π" Equivalent-Circuit Model for On-Chip Spiral Inductors

A new wideband predictive ldquodouble-pirdquo equivalent-circuit model for on-chip spiral inductors is presented, in which the model parameters are analytically calculated with layout and process parameters. In the model, five major parasitic effects, including skin effect, proximity effect, distributed effect, substrate capacitive loss, and inductive loss, are implemented together. Considering skin effect and proximity effect simultaneously, a new equation of high-frequency resistance is proposed, and accordingly, two coupled transformer loops are developed, respectively, to calculate the network parameters of skin effect, proximity effect, and substrate inductive coupling effect independently. In order to analytically calculate substrate capacitive loss in multiturn inductors, a quasi-linear relationship between capacitive coupling effect and proximity effect is established. A series of inductors with different geometries are fabricated in two standard RFCMOS processes to verify the model. Excellent agreements have been obtained between the measured data and the proposed model within a wide frequency range. Since a clear relationship between circuit components and fabrication parameters is defined, it can precisely predict the performance of the inductors and become more flexible in RFIC design.

A Wideband Predictive “Double-

A new wideband predictive ldquodouble-pirdquo equivalent-circuit model for on-chip spiral inductors is presented, in which the model parameters are analytically calculated with layout and process parameters. In the model, five major parasitic effects, including skin effect, proximity effect, distributed effect, substrate capacitive loss, and inductive loss, are implemented together. Considering skin effect and proximity effect simultaneously, a new equation of high-frequency resistance is proposed, and accordingly, two coupled transformer loops are developed, respectively, to calculate the network parameters of skin effect, proximity effect, and substrate inductive coupling effect independently. In order to analytically calculate substrate capacitive loss in multiturn inductors, a quasi-linear relationship between capacitive coupling effect and proximity effect is established. A series of inductors with different geometries are fabricated in two standard RFCMOS processes to verify the model. Excellent agreements have been obtained between the measured data and the proposed model within a wide frequency range. Since a clear relationship between circuit components and fabrication parameters is defined, it can precisely predict the performance of the inductors and become more flexible in RFIC design.