C. Camperi-Ginestet

Alignable epitaxial liftoff of GaAs materials with selective deposition using polyimide diaphragms

The authors report the selective and alignable deposition of patterned thin-film epitaxial GaAs/GaAlAs devices onto a host substrate such as silicon for low cost, manufacturable hybrid integrated optoelectronic circuits. The authors use a thin polyimide diaphragm as the transparent transfer medium for these patterned epitaxial devices. Each of these devices or a group of these devices on the polyimide is then optically aligned and selectively deposited onto the host substrate. The use of the polyimide transfer diaphragm also allows both the bottom and the top of the device to be processed while under substrate support. Using this technique, a light emitting diode 50*50 mu m in area and 2 mu m thick was grown on a GaAs substrate, lifted off, aligned and selectively deposited onto a silicon host substrate, and electrically contacted and tested.<<ETX>>

Vertical electrical interconnection of compound semiconductor thin-film devices to underlying silicon circuitry

A three-dimensional integration technology that electrically connects an independently optimized thin-film device layer to a Si circuitry layer is reported. An epitaxial liftoff GaAs thin-film optical detector is integrated directly on top of Si amplifier circuitry with a planarizing, insulating layer of polymide between the detector and the circuitry. The detector is virtually connected to the circuitry below through an electrical via in the insulator. This integration technology enables monolithic, massively parallel vertical interconnection between two independently optimized device layers. Systems such as image processing arrays should significantly benefit from this massively parallel integration technology.<<ETX>>

Vertical optical communication through stacked silicon wafers using hybrid monolithic thin film InGaAsP emitters and detectors

The authors report the first demonstration of vertical optical communication through stacked Si wafers using low-cost hybrid monolithic thin-film InGaAsP/InP emitters and detectors, designed for operation at 1.3 mu m. A thin-film InGaAsP homojunction light-emitting diode (LED) (4.5- mu m thick) was deposited onto a polished, nitride-coated Si wafer using a modified epitaxial liftoff technique. A InP/InGaAsP/InP p-i-n photodetector (4.5- mu m thick) was similarly deposited on an identically prepared Si wafer. The emitter and detector were then aligned, resulting in a stacked wafer configuration suitable for vertical through-wafer optical communication. This integration technique eliminates the need for direct growth of compound semiconductors onto Si.<<ETX>>

Communication through stacked silicon circuitry using integrated thin film InP-based emitters and detectors

To demonstrate optical communication through stacked silicon circuitry, thin film InGaAsP-based emitters and photodetectors have been bonded directly onto silicon circuitry. These optoelectronic devices operate at a wavelength to which silicon is transparent. The thin film emitters and detectors were integrated onto a MOSIS foundry silicon CMOS integrated circuit which contained driver and amplifier circuits. Bidirectional vertical optical communication between two layers of circuitry was demonstrated by stacking the layers, exciting the emitter driver circuit on one layer with an electrical signal, and measuring the output electrical signal from the detector amplifier located on the other circuit in the vertical stack.<<ETX>>

A fine-grain, high-throughput architecture using through-wafer optical interconnect

The author present a highly parallel, three-dimensionally interconnected system to process high-throughput stream data such as images. Optical interconnect at wavelengths to which silicon is transparent is used to create the 3D system. Thin film InP/InGaAsP-based emitters and detectors operating at 1.3 microns are bonded to the silicon circuitry, and emit through the silicon wafer to create the vertical optical interconnect. Foundry-fabricated Si circuits are post processed using standard, low cost, high yield microfabrication techniques to integrate the thin film devices with the circuits. In order to meet off-chip I/O requirements, a high-bandwidth, three-dimensional optical network is also being designed. Using through-wafer optical interconnect, a new offset cube topology has been created, and naming and routing schemes have been developed. Its performance is comparable to that of a three-dimensional mesh. A processing architecture has also been defined that minimizes overhead for basic parallel operations. A complete processing node for high-throughput, low-memory applications can be implemented using a fraction of a chip.<<ETX>>

Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors complicates the use of feedback circuits. Thus feedback is generally not used in the front-end of our digital process CMOS receivers.

High density focal plane signal processing using 3-D vertical interconnects

A four by four array of GaAs P-i-N photodetectors was integrated onto a metalized silicon substrate and directly on top of an array of silicon circuits. The resultant focal plane processor at each location in the array converts the incident light intensity to a logarithmically encoded frequency signal.

Three Dimensional Smart Pixel Integration Of A GaAs-based Detector Array Directly On Top Of Silicon Circuits

A smart pixel imaging array of GaAs-based thin film photodetectors has been integrated in three dimensions directly on top of silicon neuromorphic oscillator circuits. Photomicrographs of the integrated assembly and test results are presented.

Alignable Deposition of Thin Film Semiconductor Materials for Integrated Micro-Opto-Electronic Systems

The selective and alignable deposition of patterned thin film epitaxial GaAs/GaAlAs and InP/InGaAsP devices onto host substrates such as silicon for low cost hybrid integrated micro-opto-electronic systems is reported. Using a combination of semiconductor etch layers and selective etches, the epilayers can be separated from the growth substrate. We use a thin polyimide diaphragm as the transparent transfer medium for these epitaxial materials and devices. Each of these thin film devices or a group of these devices on the polyimide is optically aligned and selectively deposited onto the host substrate. Using this technique, GaAs and InP-based light emitting diodes and optical detectors which are microns thick were grown on lattice matched GaAs and InP substrates, lifted off, aligned and selectively deposited onto a silicon host substrate. The devices were then electrically contacted and tested using standard microelectronic fabrication and testing techniques. This method also enables the manufacturable, sparse distribution of costly photonic devices or the deposition of aligned arrays of devices to fabricate larger arrays. The integration of these light weight devices with micro sensors and micro actuators will foster micro-opto-electro-mechanical integration. INTRODUCTION The integration of high quality, single crystal thin film gallium arsenide (GaAs) and indium phosphide (InP) based photonic and electronic materials and devices with host substrates and structures comprised of material such as silicon (Si), glass, and polymers will enable the fabrication of the next generation of micro-opto-electro-mechanical systems and optoelectronic integrated circuits. Thin film semiconductor devices deposited onto arbitrary host substrates and structures create near-monolithic integrated systems which can be interconnected electrically using standard inexpensive microfabrication techniques such as vacuum metallization and photolithography. In particular, the low weight of these thin film devices makes them attractive for integration with micromechanical devices which may have difficulty supporting and translating the full weight of a standard device. In this paper, we discuss methods for the alignment, selective deposition, and interconnection of thin film epitaxial GaAs and InP based devices onto host substrates and host microstructures. In integrated systems, it is often advantageous to utilize a variety of materials, each suited to a particular purpose. Compound semiconductors are useful optoelectronic devices, and silicon and polymers have been widely investigated for microstructure and microelectronic systems. High quality compound semiconductor devices, particularly those suited for optoelectronic applications, are generally grown lattice matched or near lattice matched. For the integration of GaAs on Si, heteroepitaxial growth has been intensively investigated [I). However, the crystal quality of this material is often insufficient for many optical applications. To integrate compound semiconductor devices with host materials which have no periodicity, however, the compound semiconductor cannot be grown directly