C. Couso

Monte Carlo Study of Dopant-Segregated Schottky Barrier SoI MOSFETs: Enhancement of the RF Performance

This paper presents a detailed Monte Carlo study of the optimization of the dopant segregation (DS) layer in n-type Schottky barrier (SB)-MOSFET. It is shown that with a careful control of the DS layer parameters, dopant concentration (Ndop), and length (Ldop), the performance of the devices is significantly enhanced. The presence of the DS layer induces crucial effects in the injection processes at the Schottky contacts. The benefits of increasing the length and the doping level of the DS layer are studied from the microscopic point of view (transit times, average number of scatterings). The effect of varying these parameters is also analyzed through the nonquasi-static parameters of the small signal equivalent circuit, which can be useful for designers to improve the reliability of the SB-MOSFET technology.

A Monte Carlo Study of electron transport in suspended monolayer graphene

A microscopic study of electronic transport in suspended monolayer graphene is presented. The results have been obtained by means of an ensemble Monte Carlo simulator that takes into account the main physical properties of the graphene bandstructure and the most relevant scattering mechanisms for this type of material. The carrier velocity value is mainly set by the dominant influence of optical and acoustic intervalley phonons, particularly at high electric fields, where a negative differential conductance is observed. The average time between scatterings shows an asymptotic behavior with the applied electric field, with values in the order of tenths of ps. The influence of the electric field on the wavevector distribution is also analyzed, showing a saturation trend in the displacement of the charge centroid with a linear increase in the average energy. Finally, the instantaneous velocity and the correlation function of velocity fluctuations are also studied.

CAFM Experimental Considerations and Measurement Methodology for In-Line Monitoring and Quantitative Analysis of III–V Materials Defects

To continue technology scaling, a new generation of high-performance devices are considered to be implemented using III-V semiconductors, which need to be grown over the conventional Si substrate. However, due to the lattice mismatch between the III-V and silicon materials, the former tend to develop significant density of structural defects [specifically, threading dislocations (TDs)], which can adversely affect device electrical characteristics. Conductive atomic force microscope (CAFM) technique is among the most promising tools for the identification and analysis of TDs in a nanoscale range although obtaining reliable quantitative data requires precise controls over the measurements conditions. In this study, CAFM technique has been applied for TDs detection and analysis in III-V films, and tool requirements and measurement methodology are discussed.

Conductance of Threading Dislocations in InGaAs/Si Stacks by Temperature-CAFM Measurements

The stacks of III-V materials, grown on the Si substrate, that are considered for the fabrication of highly scaled devices tend to develop structural defects, in particular threading dislocations (TDs), which affect device electrical properties. We demonstrate that the characteristics of the TD sites can be analyzed by using the conductive atomic force microscopy technique with nanoscale spatial resolution within a wide temperature range. In the studied InGaAs/Si stacks, electrical conductance through the TD sites was found to be governed by the Poole-Frenkel emission, while the off-TDs conductivity is dominated by the thermionic emission process.

Threading dislocations in III-V semiconductors: Analysis of electrical conduction

The implementation of devices with high mobility substrates requires growing III-V semiconductors over the underlying silicon substrates. However, due to the lattice mismatch, III-V materials tend to develop a significant density of structural defects, which may affect the device electrical characteristics. In this study, Threading Dislocation (TD) defects, which may propagate through the III-V layers, were studied using Conductive Atomic force Microscopy (CAFM). This technique is shown to be effective for identification and analysis at the nanoscale of the pre- and post-electrically stressed TD. The TD conduction studied at different temperatures (T) is shown to be consistent with the Poole-Frenkel (PF) emission process.

Conductive-AFM topography and current maps simulator for the study of polycrystalline high-k dielectrics

In this work, a simulator of conductive atomic force microscopy (C-AFM) was developed to reproduce topography and current maps. In order to test the results, the authors used the simulator to investigate the influence of the C-AFM tip on topography measurements of polycrystalline high-k dielectrics, and compared the results with experimental data. The results show that this tool can produce topography images with the same morphological characteristics as the experimental samples under study. Additionally, the current at each location of the dielectric stack was calculated. The quantum mechanical transmission coefficient and tunneling current were obtained from the band diagram by applying the Airy wavefunction approach. Good agreement between experimental and simulation results indicates that the tool can be very useful for evaluating how the experimental parameters influence C-AFM measurements.

Effect of the dopant segregation layer on the static characteristics of Schottky-barrier n-MOSFETs

This paper presents a detailed investigation of the impact of dopant segregation (DS) on the static characteristics performance of n-type 120-nm ultrathin-body Schottky-barrier (SB) silicon-on-insulator MOSFETs. The optimization of the dopant concentration (NDOP) and lateral extension (LDOP) of the DS layer is studied. A careful choice of these quantities reduces the effective potential barrier height at the Schottky junctions, boosting the drive current and transconductance. Important effects are also observed in internal quantities related to electronic transport like velocity, energy and carrier concentration within the channel. These enhancements in SB-MOSFET devices featuring DS layers confirm the suitability of this technology to help extending the roadmap for Silicon MOS devices.

Nanoscale electrical characterization of a varistor-like device fabricated with oxidized CVD graphene

The electrical properties of an electron device that contains CVD graphene with oxidized grain boundaries are presented. We found that the device behaves as a varistor. The topographical and electrical properties of the graphene layer were studied at the nanoscale with CAFM and KPFM. The results confirm that the morphology and properties of the oxidized grain boundaries can be the origin for the device level characteristics and the device-to-device variability. Because of the properties of the analyzed structures, this device could be used in potential fully-2D materials based circuits.

Dependence of MOSFETs threshold voltage variability on channel dimensions

The dependence of the MOSFET threshold voltage variability on device geometry (width (W) and length (L)) has been studied from experimental data. Our results evidence, in agreement with other works, deviations from the Pelgroms rule, especially in smaller technologies. TCAD simulations were also performed which further support the experimental data and provide physical information regarding the origin of such deviation. Finally, a new empirical model that assumes different impact of W and L in the device variability has been proposed, which reproduces the experimental results.

Threshold voltage and on-current Variability related to interface traps spatial distribution

Interface traps can be a source of variability in MOSFETs, leading to statistically distributed electrical characteristics of devices. This work discusses, from 3D TCAD simulations, the effect of the spatial distribution of interface traps on the variability of the threshold voltage and the on-current of MOSFETs. The results suggest that threshold voltage is mainly influenced by the trap distribution along the channel of the device, whereas on-current is also influenced by the alignment of the traps along the device width. Implications for device electrical symmetry are discussed.