Singh Jagar

Super thin-film transistor with SOI CMOS performance formed by a novel grain enhancement method

High performance super TFTs with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decreases significantly when the device is scaled down, resulting in better device performance and higher uniformity.

Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization

Metal-induced-lateral-crystallization (MILC) followed by high temperature annealing has been used for the first time to form, large single grain silicon from amorphous silicon. Polysilicon with grain size ranging from ten to hundred of microns can be formed by this method. By individually crystallizing the active area of a TFT, the entire transistor can be formed on a single or a small number of silicon grains with good controllability, thus similar to SOI structure. Test devices with thin t/sub ox/=120 /spl Aring/ have been fabricated and the performance is verified to be comparable to SOI MOSFETs. The scaling property of the grain enhanced TFTs has also been studied. The minimization of the device dimension results in smaller probability for the channel region of a TFT to cover multiple grains, which leads to better device performance.

Submicron super TFTs for 3-D VLSI applications

High performance submicron super TFTs are reported. A novel grain enhancement method is used to form large single grain silicon at the channel region of the TFT, making its structure comparable to SOI MOSFET. The process can be performed with high controllability, thus giving much smaller device-to-device variation compared to conventional TFT process. The reported n-channel super TFT displays a subthreshold swing of 72 mV/dec, g/sub max/=198 mS/mm and an I/sub dast/ of 0.3 mA//spl mu/m at V/sub g/-V/sub t/=1.5 V, with L/sub G/=0.4 /spl mu/m and t/sub ox/=110 /spl Aring/. The super TFT technology will facilitate the formation of three-dimensional (3-D) VLSI circuits and double gate CMOS.

Effects of longitudinal and latitudinal grain boundaries on the performance of large-grain polysilicon MOSFET

The effects of longitudinal and latitudinal polysilicon grain boundaries on the performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. Unlike conventional thin-film-transistors (TFTs) with random grain distribution, MOSFETs fabricated on the LPSOI film contains the combination of only longitudinal or latitudinal grain boundaries. Longitudinal GBs parallel to the direction of current flow has smaller impact to the current flow, but provided extra leakage current that caused early device shortage, especially in wide devices. The latitudinal GBs perpendicular to the direction of current flow offered higher resistance to the inversion carriers thus causing lower current drive, higher threshold voltage, and gentler subthreshold slope. The result of the study can be used to optimize device design for high performance on MOSFETs on the LPSOI substrate.

A SPICE model for thin-film transistors fabricated on grain-enhanced polysilicon film

A simulation program with integrated circuit emphasis (SPICE)-compatible thin-film transistor (TFT) model for TFTs formed on grain-enhanced polysilicon (poly-Si) film by metal-induced-unilateral crystallization (MIUC) is presented. Due to the regularity of grain structures resulting from the MIUC process, the GBs are organized into a manhattan grid. The specific grain boundary (GB) organization allows a physics-based model to be developed. The model is based on the popular BSIM3 submicron CMOS model framework, which captures most of the physical effects in both long channel and short channel down to the submicron dimension. The model has been verified by a large amount of experimental data and shown to be applicable over a wide range of TFT processes with the application of grain-enhancement techniques such as solid-phase crystallization (SPC) and MIUC.

Characterization of MOSFETs fabricated on large-grain polysilicon on insulator

Abstract Large-grain polysilicon on insulator films, formed by utilizing metal induced unilateral crystallization (MIUC) of amorphous silicon film and subsequent high temperature annealing, has been used to fabricate high performance MOSFETs. The corelation between the improvement of device characteristics and of grain size enhancement has been studied. It was found that the MOSFET characteristics have a strong dependence on both device width and length. Substantially better characteristics of devices fabricated on the enhanced films compared with other recrystallization methods are observed in large devices. Significant improvement in device characteristics has been demonstrated as the dimension is reduced. The statistical variation on device parameters has also been studied and the most significant device-to-device variation is found when the transistor size is around the size of the silicon grains.

A statistical model to predict the performance variation of polysilicon TFTs formed by grain-enhancement technology

A statistical model to predict grain boundary distribution in the channel of a polysilicon thin-film transistor (TFT) is proposed. The model is valid for arbitrary transistor size to grain size ratio, and is particularly useful to predict the grain boundary distribution of recrystallized large-grain polysilicon TFTs where the transistor size is comparable to the grain size and gives significant device-to-device variation. The model has been extensively verified by comparing it with statistical data obtained from TFTs fabricated using metal-induced-lateral-crystallization and regular solid-phase epitaxial techniques. Good agreements between the experimental results and model prediction are demonstrated.

Design methodology of the high performance large-grain polysilicon MOSFET

A methodology to design high-performance MOSFETs on the large-grain polysilicon-on-insulator (LPSOI) film is presented. Due to the metal-induced lateral crystallization (MILC) process in the formation of LPSOI films, the polysilicon grain locations and orientations can be reasonably controlled. Therefore, the performance of an LPSOI MOSFET can be optimized by carefully selecting the orientation and grain location according to the size of the desired transistor. The effects of various design parameters including the distance from the nickel strip, relative source/drain position, transistor orientation, and layout geometry are investigated. A ladder layout method is proposed to provide scalability in the design of high performance LPSOI MOSFETs. A design guideline for designing LPSOI NMOSFETs with different dimensions is given.

SOI formation from amorphous silicon by metal-induced-lateral-crystallization (MILC) and subsequent high temperature annealing

In current SOI technology, the formation of circuit elements requires the use of some special starting material like SIMOX, BESOI or Unibond wafers, which usually cannot be made in-house. As such, it leads to a divergence between SOI technology and bulk technology, and there are debates on justification on the initial material cost. TFTs formed in polysilicon have similar structures to SOI, and have been used as the load element in SRAM. Comparing TFT and SOI transistors, the TFT is easier to fabricate in term of starting material and compatibility with bulk processes. However, its performance is usually very poor for high performance circuits. The TFT structure consists of a large number of small size crystallized silicon grains. It is desirable to have a very large grain size so that a single transistor can lie entirely on a single grain. In this case, the TFT becomes an SOI MOSFET. Metal-induced-lateral-crystallization (MILC) has been used to enlarge the polysilicon TFT grain size. However, due to the limitation in low temperature formation, the grain size is still not desirable. With the use of high temperature annealing at a temperature above 900/spl deg/C after MILC, we found that much larger crystals of the order of 10 /spl mu/m can be formed. For the advanced technology which comes with device scaling, it is possible to individually recrystallize the active region of each transistor, giving TFTs (as formed) with SOI MOSFET performance.

Analysis of aligned polysilicon grain boundaries effects on the performance of large-grain polysilicon MOSFET

Aligned polysilicon grain boundaries effects on the performance of the MOSFET fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. The LPSOI film of grain size ranging from 10 to 100 /spl mu/m is formed from amorphous silicon using MILC (metal induced lateral crystallization) and subsequent high temperature annealing. The grain boundaries (GBs) are found parallel to the crystallization direction and it is possible to align these GBs parallel (longitudinal) and perpendicular (latitudinal) to the direction of current flow in the channel region. The parallel GBs have shown minimum impedance to the conduction carriers, thus the parallel GBs devices are maintaining the high drive current, low threshold voltage, and steep subthreshold slope. However, it is the source of higher leakage current in the off-state, which causes an early device shortage especially in wide devices. On the other hand, perpendicular GBs in the channel region have shown high impedance to the conduction carriers that result in higher threshold voltage, lower current drive, and gentle subthreshold slope. A significant improvement in the device performance his been obtained with scaling. This analysis provides the guideline for the high performance LPSOI circuits for 3-D application.