C. Huffman

Thermally Stable N-Metal Gate MOSFETs Using La-Incorporated HfSiO Dielectric

We report a thermally stable N-metal process in which surface passivation of HfSiO dielectric using thin layers of La₂O₃, deposited by either MBE or PVD, significantly shifts the metal gate effective work function toward the Si conduction band edge. Well-behaved transistors with L_g down to 70 nm have been fabricated with threshold voltage of 0.25V, mobility up to 92% of the universal SiO₂ mobility, and T_inv ~1.6 nm

Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration

This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel Vt of ~plusmn0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT<1/spl Aring/). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L/sub g/ down to 85nm.

Thermal response of Ru electrodes in contact with SiO2 and Hf-based high-k gate dielectrics

A systematic experimental evaluation of the thermal stability of Ru metal gate electrodes in direct contact with SiO2 and Hf-based dielectric layers was performed and correlated with electrical device measurements. The distinctly different interfacial reactions in the Ru∕SiO2, Ru∕HfO2, and Ru∕HfSiOx film systems were observed through cross-sectional high-resolution transmission electron microscopy, high angle annular dark field scanning transmission electron microscopy with electron-energy-loss spectra, and energy dispersive x-ray spectra analysis. Ru interacted with SiO2, but remained stable on HfO2 at 1000°C. The onset of Ru∕SiO2 interfacial interactions is identified via silicon substrate pitting possibly from Ru diffusion into the dielectric in samples exposed to a 900°C∕10-s anneal. The dependence of capacitor device degradation with decreasing SiO2 thickness suggests Ru diffuses through SiO2, followed by an abrupt, rapid, nonuniform interaction of ruthenium silicide as Ru contacts the Si substrate. ...

Sub-100 nm InGaAs quantum-well (QW) tri-gate MOSFETs with Al 2 O 3 /HfO 2 (EOT < 1 nm) for low-power logic applications

This paper reports tri-gate sub-100 nm In_0.53Ga_0.47As QW MOSFETs with electrostatic immunity of S = 77 mV/dec., DIBL = 10 mV/V, together with excellent carrier transport of g_{m, max} > 1.5 mS/μm, at V_DS = 0.5 V. This result is the best balance of g_{m, max} and S in any reported III-V MOSFETs. In addition, extracted compact model parameter including (μ₀ = 760 cm²/V-s and peak v_x0 = 1.6×10⁷ cm/s) indicate that InGaAs Tri-Gate MOSFETs would be a viable pathway to sub-10nm technology node.

STLM: A Sidewall TLM Structure for Accurate Extraction of Ultralow Specific Contact Resistivity

We propose a very large scale integration compatible, modified transfer length method (TLM) structure, called sidewall TLM, to minimize the effect of spreading resistance and thus improving the resolution of the TLM method. This is achieved by allowing uniform current collection perpendicularly through the sidewall of the contact. We demonstrate statistically significant specific contact resistivity (ρ_c) extraction of 2×10^-8Ω cm² and 5×10^-9Ω cm² for n-type and p-type NiSi contacts, respectively, on a 300-mm wafer, which are about 50% less than those extracted using the conventional TLM structure. The proposed structure also shows a tighter distribution in the extracted ρ_c values. The results show the importance of such test structures to accurately extract ultralow ρ_c values relevant to sub-14-nm technology nodes.

VLSI processed InGaAs on Si MOSFETs with thermally stable, self-aligned Ni-InGaAs contacts achieving: Enhanced drive current and pathway towards a unified contact module

Parasitic resistance (Rpara) is a grand challenge to successfully hetero-integrate III-V channels onto Si for CMOS application. Here, we report the first statistical IDsat comparison for non-self-aligned and self-aligned contacts of In0.53Ga0.47As MOSFETs fabricated on large scale Si substrates with VLSI toolsets. We compare non-self-aligned Mo and self-aligned Ni-InGaAs contacts. Devices with self-aligned contacts exhibit a 25% enhancement in IDsat over devices with non-self-aligned contacts largely due to the 27% reduction in Rpara. We have also extended the thermal stability of Ni-InGaAs to 500 °C (highest reported) enabling it to be compatible with BEOL processes. The impact of the Ni-InGaAs process module on tool contamination is discussed. These results represent significant progress towards establishing a path to a unified Ni-based S/D contact module for Si/SiGe/Ge/III-V co-integration on VLSI platforms.

Improved Gate-Edge Profile of Metal/High-k Gate Stack Using an NH3 Ashing Process in Gate-First CMOSFETs

This study analyzed an alternative ashing technology for removing photoresist in the production of gate-first complementary metal oxide semiconductor field effect transistors (CMOSFETs) with a high-k metal gate stack. NH 3 ashing is proposed as an alternative to O 2 ashing to improve the gate-edge profile. It was found that NH 3 ashing suppresses bottom oxide growth below the thin HfO 2 layer, reducing Si recesses in the source/drain active area, and eliminating bottom oxide encroachment into the gate edge. The NH 3 ashing process also makes the HfO 2 film more resistant to the wet chemistry, which reduces the high-k undercut beneath the metal gate during the high-k removal process.

Ultra low contact resistivity ( −8 Ω-cm 2 ) to In 0.53 Ga 0.47 As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

We report a record low contact resistivity of sub-1.0×10^-8 Ω.cm² realized on n⁺ In_0.53Ga_0.47As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to eliminate implant damage in III-V fins. This increased activation efficiency (+3.6×) and reduced sheet resistance (-60%).

Challenges of III–V materials in advanced CMOS logic

The superior transport properties of III-V materials are promising candidates to achieve improved performance at low power. This paper examines the module challenges of III-V materials in advanced CMOS at or beyond the 10 nm technology node, and reports VLSI compatible epi, junction, contact and gate stack process modules with Xj<;60;10nm, N_D=5×10¹⁹ cm^-3, ρ_c= 6Ω.μm² and Dit = 4×10¹² eV^-1 cm^-2. Si VLSI fab and ESH protocols have been developed to enable advanced process flows.