Joel Barnett

The effect of interfacial layer properties on the performance of Hf-based gate stack devices

The influence of Hf-based dielectrics on the underlying SiO2 interfacial layer (IL) in high-k gate stacks is investigated. An increase in the IL dielectric constant, which correlates to an increase of the positive fixed charge density in the IL, is found to depend on the starting, pre-high-k deposition thickness of the IL. Electron energy-loss spectroscopy and electron spin resonance spectra exhibit signatures of the high-k-induced oxygen deficiency in the IL consistent with the electrical data. It is concluded that high temperature processing generates oxygen vacancies in the IL responsible for the observed trend in transistor performance.

Nucleation and growth study of atomic layer deposited HfO2 gate dielectrics resulting in improved scaling and electron mobility

HfO2 films have been grown with two atomic layer deposition (ALD) chemistries: (a) tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and (b) HfCl4+H2O. The resulting films were studied as a function of ALD cycle number on Si(100) surfaces prepared with chemical oxide, HF last, and NH3 annealing. TEMAHf+O3 growth is independent of surface preparation, while HfCl4+H2O shows a surface dependence. Rutherford backscattering shows that HfCl4+H2O coverage per cycle is l3% of a monolayer on chemical oxide while TEMAHf+O3 coverage per cycle is 23% of a monolayer independent of surface. Low energy ion scattering, x-ray reflectivity, and x-ray photoelectron spectroscopy were used to understand film continuity, density, and chemical bonding. TEMAHf+O3 ALD shows continuous films, density >9g∕cm3, and bulk Hf–O bonding after 15 cycles [physical thickness (Tphys)=1.2±0.2nm] even on H-terminated Si(100). Conversely, on H-terminated Si(100), HfCl4+H2O requires 50 cycles (Tphys∼3nm) for continuous films and bulk Hf–O bonding. ...

Imaging local electronic corrugations and doped regions in graphene

Electronic structure heterogeneities are ubiquitous in two-dimensional graphene and profoundly impact the transport properties of this material. Here we show the mapping of discrete electronic domains within a single graphene sheet using scanning transmission X-ray microscopy in conjunction with ab initio density functional theory calculations. Scanning transmission X-ray microscopy imaging provides a wealth of detail regarding the extent to which the unoccupied levels of graphene are modified by corrugation, doping and adventitious impurities, as a result of synthesis and processing. Local electronic corrugations, visualized as distortions of the π*cloud, have been imaged alongside inhomogeneously doped regions characterized by distinctive spectral signatures of altered unoccupied density of states. The combination of density functional theory calculations, scanning transmission X-ray microscopy imaging, and in situ near-edge X-ray absorption fine structure spectroscopy experiments also provide resolution of a longstanding debate in the literature regarding the spectral assignments of pre-edge and interlayer states.

Interfacial Layer-Induced Mobility Degradation in High-

Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

k

Nitrogen incorporation in HfO2∕SiO2 films utilized as high-k gate dielectric layers in advanced metal-oxide-semiconductor field effect transistors has been investigated. Thin HfO2 blanket films deposited by atomic layer deposition on either SiO2 or NH3 treated Si (100) substrates have been subjected to NH3 and N2 anneal processing. Several high resolution techniques including electron microscopy with electron energy loss spectra, grazing incidence x-ray diffraction, and synchrotron x-ray photoelectron spectroscopy have been utilized to elucidate chemical composition and crystalline structure differences between samples annealed in NH3 and N2 ambients as a function of temperature. Depth profiling of core level binding energy spectra has been obtained by using variable kinetic energy x-ray photoelectron spectroscopy with tunable photon energy. An “interface effect” characterized by a shift of the Si4+ feature to lower binding energy at the HfO2∕SiO2 interface has been detected in the Si 1s spectra; however,...

Transistors

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moores Law towards the 10-nm physical gate length regime.

Chemical analysis of HfO2∕Si (100) film systems exposed to NH3 thermal processing

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

High-k gate stacks for planar, scaled CMOS integrated circuits

Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

We present the first demonstration of a III–V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III–V and Si devices can be processed side by side in the same Si fabrication line The L<inf>g</inf> = 500 nm device has a excellent drive current of ∼450 µA/µm and intrinsic transconductance of ∼1000 µS/µm indicating that III–V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

Band-Engineered Low PMOS V T with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

We demonstrate for the first time, a 20nm FinFET using a new, conformal, and damage-free monolayer doping technique. Unlike conventional ion-implantation, this approach makes use of a dopant-containing precursor to uniformly assemble a monolayer of covalently bonded dopants to enable an ultra-shallow (Xj∼5nm) and abrupt (0.6nm/dec) junction formation around a high aspect ratio fin structure, which overcomes the possible FinFET pitch scaling limitations of traditional doping techniques. FinFETs featuring MLD junctions were successfully demonstrated with good electrostatics control down to a gate length of ∼40nm. With further scaling of the fin width, sub-threshold swing and threshold voltage roll-off can be further improved. This low damage and conformal doping is a promising technique to address key FinFET scaling issues associated with parasitic series resistance and short channel control for the 15nm node and beyond.