M. R. Tajari Mofrad

Integrated high performance (100) and (110) oriented single-grain Si TFTs without seed substrate

We report high performance (100) and (110) oriented single-grain thin-film-transistors (SG-TFTs) fabricated below 600°C without any seed substrate. The orientation has been contolled by ¼-Czochralski process with the excimer laser. Field-effect mobility of n-channel transistor is 998cm²/Vs for (100) SG-TFTs and 811cm²/Vs for (110) SG-TFTs. Field-effect mobility of p-channel transistor is 292cm²/Vs for (100) SG-TFT and 429cm²/Vs for (110) SG-TFTs.

High performance single-grain Ge TFTs without seed substrate

We report high performance single-grain Ge TFTs by μ-Czochralski process. Electron mobilites are 3337cm²/Vs with on/off ratio of 10⁸ @V<inf>DS</inf>=0.1V. Hole mobilities are 1719cm²/Vs with on/off ratio of 10⁸ @V<inf>DS</inf>=0.05V. The high mobility is due to improved interface property and tensile stress.

Analog and digital output lateral photodiodes fabricated by µ-Czochralski process at low temperature

We have designed and fabricated lateral photodiodes with analog and digital outputs using µ-Czochralski process. The advantage of µ-Czochralski process is crystallization of active silicon layer at low temperature using Excimer laser. In this process, predefined locations on oxide with 1µm squares, called grain filters, are formed to determine the locations of single grain silicon. Then these holes are covered by 870nm PECVD TEOS oxide at 350°C to reduce the size of holes to approximately 0.1µm. After deposition of 250nm LPCVD amorphous silicon at 550°C, Excimer laser is irradiated on silicon at 400°C with 1500mJ/cm2 laser energy. This laser energy can give uniform square grains before ablation. It melts the silicon layer and then crystallization starts from bottom of grain filter where we have solid and un-melted silicon. This technique is suitable for stacking silicon layers to realize monolithic 3DIC. Fabricated TFTs inside single grains are comparable with SOI devices in term of high mobility and high frequency behavior characteristics. [1] The achieved motilities are 500cm2/VS for nMOS and 300cm2/VS for pMOS transistors. Figure 1 shows the schematics of this process and also SEM image of crystallized silicon. The size of grains is more sensitive to laser energy and in average they are in 6µm squares.

Single Grain Si TFTs for RF and 3D ICs

Single-grain Si TFTs have been fabricated using accurate 2D location control of large Si grain with the ?-Czochralski process. TFTs fabricated inside the crystalline islands of 6 ?m show a mobility (600cm2/Vs) as high as that of the SOI counterpart, despite of the low-temperature (<350oC) process. By applying a tensile stress into the grain, the mobility surpass even the SOI counterparts. We have succeeded in controlling crystallographic orientation of the location-controlled Si grains as well, by combination of metal induced lateral crystallization and the micro-Czochralski process. Owing to the orientation control, uniformity in device properties approaches to the level of the SOI counterpart. Using the high performance single-grain (SG) Si TFTs, we have fabricated RF amplifier. The cut-off frequency of the RF device is 5.5 GHz with a channel length of 1.5 ?m. We have even succeeded to stack two SG-TFT layers with which CMOS inverters were fabricated. This will open several new applications in TFTs of RF wireless communication, 3D-ICs with device level integration, and flexible electronics.

Pulsed-Laser-Induced Epitaxial Growth of Silicon for Three-Dimensional Integrated Circuits

Pulsed-Laser-induced epitaxial growth (PLEG) is an attractive method for lateral overgrowth of orientation-controlled silicon (Si). As underlying MOS-FETs on the seeding crystalline Si wafer is not thermally damaged, the PLEG is promising for monolithic 3D integration of circuits. This paper will review our systematic studies of both simulation and experiment on the PLEG of Si aimed for fundamental understanding of the epitaxial growth and reduction of defect generation. Experimentally a XeCl excimer-laser irradiates the sample which consists of amorphous-silicon (a-Si) deposited on a thick SiO2 with a small contact opening on a 〈100〉 oriented SOI or bulk-Si wafer. The experiment verified our 2D transient heat transfer simulation results that the combination of the long-pulse and the bulk-Si wafer gives the widest process window. The bulk-Si wafer seeding provided the larger Si island size of 6 μm than that of the SOI (4 μm). From Electron Backscattering Diffraction (EBSD) analysis it was found that 〈100〉 is the main surface crystallographic orientation. However there exist four, isolated secondary sub-grains inside the Si island. TEM cross-sectional image revealed formation of the subgrains due to formation of Σ3 (111) type of coincident site lattice (CSL) boundary originated at the SiO2 sidewall. We believe that the gentle slope of the side wall allows the extension of the facet to the CSL boundary and subgrains. At last we introduced a way to reduce the CSL boundary formation in the PLEG of Si. By using 75∘ steep sidewalls of the opening to the seed, we have successfully obtained an array of Si islands having a size of 4 μm with {100} surface orientation only, without any subgrains inside.

Location- and orientation-controlled, large single grain silicon induced by pulsed excimer laser crystallization

We studied pulsed laser induced epitaxy of silicon using a seeding wafer to realize location-and orientation-control of silicon grain. Silicon grains as large as 4 µm × 4 µm with mostly the preferred (100) orientation area were obtained on top of contact openings through SiO2 to seeding silicon (100) wafer. The orientation of the seed is inherited by a-Si during the solidification phase of molten-Si. The maximum process temperature of this process is 545 °C which is for LPCVD deposition of a-Si. This layer is suitable for high mobility SOI CMOS devices which serve as building blocks for monolithic 3D integration.