Se Jong Rhee

The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode

Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO/sub 2/. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be like hafnium-silicon-oxynitride (HfSiON) while the IL of the HfO/sub 2/ films seemed to be hafnium-silicate (HfSiO). HfON showed an increase of 300/spl deg/C in crystallization temperature compared to HfO/sub 2/. Dielectric constants of bulk and interface layer of HfON were 21 and 14, respectively. The dielectric constant of interfacial layer in HfON (/spl sim/14) is larger than that of HfO/sub 2/ (/spl sim/7.8). HfON dielectrics exhibit /spl sim/10/spl times/ lower leakage current (J) than HfO/sub 2/ for the same EOTs before post-metal anneal (PMA), while /spl sim/40/spl times/ lower J after PMA. The improved electrical properties of HfON over HfO/sub 2/ can be explained by the thicker physical thickness of HfON for the same equivalent oxide thickness (EOT) due to its higher dielectric constant as well as a more stable interface layer. Capacitance hysteresis (/spl Delta/V) of HfON capacitor was found to be slightly larger than that of HfO/sub 2/. Without high temperature forming gas anneal, nMOSFET with HfON gate dielectric showed a peak mobility of 71 cm/sup 2//Vsec. By high temperature forming gas anneal at 600/spl deg/C, mobility improved up to 256 cm/sup 2//Vsec.

Metal gate-HfO/sub 2/ MOS structures on GaAs substrate with and without Si interlayer

In this letter, we studied the effects of post-deposition anneal (PDA) time and Si interface control layer (ICL) on the electrical characteristics of the MOS capacitor with high-/spl kappa/ (HfO/sub 2/) material on GaAs. Thin equivalent oxide thickness (EOT<3 nm) with excellent capacitance-voltage (C-V) characteristics has been obtained. The thickness of the Si ICL and PDA time were correlated with C-V characteristics. It was found that high temperature Si ICL deposition and longer PDA time at 600/spl deg/C improved the C-V shape, leakage current, and especially frequency dispersion (<5%).

Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress

The V/sub th/ instability of nMOSFET with HfSiON gate dielectric under various stress conditions has been evaluated. It is shown that after constant voltage stress, the threshold voltage (V/sub th/) relaxes to its initial prestress value. The relaxation rate is strongly affected by the stress duration and magnitude rather than injected charge flux or magnitude of the V/sub th/ shift. It is proposed that spatial distribution of trapped charges, which is strongly affected by the stress conditions, determines the relaxation rate. The implications of the electron trapping/detrapping processes on electrical evaluation of the high-/spl kappa/ gate dielectrics are discussed.

High-k dielectrics and MOSFET characteristics

High dielectric constant materials have been investigated for gate dielectric applications. In this paper, various techniques (e.g. optimization of interfacial layer, N and Si incorporation and optimized profiles, forming gas anneal) for improving channel mobility, EOT scaling and reliability of high-k devices is discussed.

Structural advantage for the EOT scaling and improved electron channel mobility by incorporating dysprosium oxide (Dy/sub 2/O/sub 3/) into HfO/sub 2/ n-MOSFETs

A structural approach of fabricating laminated Dy₂O₃-incorporated HfO₂ multimetal oxide dielectric has been developed for high-performance CMOS applications. Top Dy₂O₃ laminated HfO₂ bilayer structure shows the thinnest equivalent oxide thickness (EOT) with a reduced leakage current compared to HfO₂. This structure shows a great advantage for the EOT scaling CMOS technology. Excellent electrical performances of the Dy₂O₃/HfO ₂ multimetal stack oxide n-MOSFET such as lower V_T, higher drive current, and an improved channel electron mobility are reported. Dy₂O₃/HfO₂ sample also shows a better immunity for V_t instability and less severe charge trapping characteristics. Two different rationed Dy ₂O₃/HfO₂ and HfO₂ n-MOSFET were measured by charge-pumping technique to obtain the interface state density (D_it), which indicates a reasonable and similar interface quality. Electron channel mobility is analyzed by decomposing into three regimes according to the effective field. Reduced phonon scattering is found to be the plausible mechanism for higher channel mobility

Optimized NH/sub 3/ annealing Process for high-quality HfSiON gate oxide

Optimization of fabrication process in obtaining high-quality HfSiON gate-oxide metal-oxide semiconductor field-effect transistors (MOSFETs) by NH/sub 3/ post-deposition anneal (PDA) has been performed. At 600/spl deg/C anneal temperature, a longer anneal duration resulted in reduced leakage current density (J), reduced trapped charges, and lower hysteresis in capacitance-voltage curves, but with a slight increase in effective oxide thickness (EOT). Subsequent interfacial layer growth with longer anneal duration was attributed to the increase in EOT. MOSFET, fabricated by the optimized process of 600/spl deg/C, 40 s NH/sub 3/ PDA, showed superior I/sub d/--V/sub d/ (drain current-drain voltage) and charge-trapping characteristics as compared to control Hf-Silicate.

Improved electrical and material characteristics of hafnium titanate multi-metal oxide n-MOSFETs with ultra-thin EOT (/spl sim/8 /spl Aring/) gate dielectric application

A novel approach of fabricating laminated TiO/sub 2//HfO/sub 2/ bi-layer multi-metal oxide dielectric was developed for high performance CMOS applications. Both layers showed negligible intermixing and no silicide formation. For the first time, ultra-thin EOT (/spl sim/8 /spl Aring/) was achieved with increased effective permittivity (k /spl sim/ 36) using the bi-layer dielectric. Leakage current characteristic was slightly higher than HfO/sub 2/ due to lower band offset of TiO/sub 2/. However, superior thermal stability (>950/spl deg/C), significantly reduced hysteresis characteristic, and comparable interface state density represent the high quality of TiO/sub 2//HfO/sub 2/ multi-metal oxide. Also, excellent subthreshold swing, increased transconductance, higher current drive, and -33% improved channel electron mobility compared to the control HfO/sub 2/ samples demonstrate the feasibility of new multi-metal oxide application for future CMOS technology.

Effects of varying interfacial oxide and high-k layer thicknesses for HfO2 metal–oxide–semiconductor field effect transistor

A metal–oxide–semiconductor capacitor and field effect transistor with a hafnium oxide (HfO2) dielectric have been fabricated. Various thicknesses of interfacial oxide and HfO2 film have been used. The results show that the flatband voltage changed due to the change in the physical thickness of the HfO2 film, and not that of the interfacial oxide layer. In addition, the effective channel electron mobility depends on both the amount of fixed charges and the distance from the fixed charges to the Si surface. The results also suggest that the fixed charges are rather uniformly distributed throughout the bulk of high-k layer.

Nickel-silicide phase effects on flatband voltage shift and equivalent oxide thickness decrease of hafnium silicon oxynitride metal-silicon-oxide capacitors

This Letter reports the nickel-silicide phase effects on the electrical characteristics of high-k and silicon dioxide (SiO2) metal-oxide-semiconductor devices. It was found that the silicon-deficient nickel-silicided gate electrode on the hafnium silicon oxynitride (HfSiON) led to a positive flatband voltage (Vfb) shift and a reduction in the equivalent oxide thickness (EOT). However, negligible Vfb shift and EOT decrease were observed in the case of control hafnium oxide and SiO2 structures. It was believed that Si dissociation from the HfSiON layer was the main reason for the positive Vfb shift and the EOT decrease.

Hafnium Titanate bilayer structure multimetal dielectric nMOSCAPs

A novel approach of fabricating laminated TiO/sub 2//HfO/sub 2/ bilayer multimetal oxide dielectric has been developed for high-performance CMOS applications. Ultrathin equivalent oxide thickness (/spl sim/8 /spl Aring/) has been achieved with increased effective permittivity (k/spl sim/36). Hysteresis was significantly reduced using the bilayer dielectric. Top TiO/sub 2/ layer was found to induce effective negative charge from the flatband voltage shift. Leakage current characteristic was slightly higher than control HfO/sub 2/, and this is believed to be due to the lower band offset of TiO/sub 2/. However, the interface state density of this bilayer structure was found to be similar to that of HfO/sub 2/ MOSCAP because the bottom layer is HfO/sub 2/. These results demonstrate the feasibility of new multimetal dielectric application for future CMOS technology.