Giovanni Mangraviti

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication

The link budget of multi-Gb/s wireless communication systems around 60GHz improves by beamforming. CMOS realizations for this type of communication are mostly limited to either one-antenna systems [1], or beamforming ICs that do not implement all radio functions [2]. The sliding-IF architecture of [3] uses RF phase shifting, which deteriorates noise performance.

A 52–66GHz subharmonically injection-locked quadrature oscillator with 10GHz locking range in 40nm LP CMOS

A mm-wave subharmonically injection-locked quadrature oscillator is demonstrated in a 40nm low-power (LP) digital CMOS technology. A large locking range (10GHz), tunable over the 52-66GHz band, is achieved using transformer-coupled resonators. A simple calibration scheme is proposed that only relies on a relative power measurement of the oscillator output signal. The wide locking range, the wide tunability and the simple calibration scheme make this injection-locked quadrature oscillator design suitable for frequency synthesis in mm-wave CMOS communication systems.

CMOS low-power transceivers for 60GHz multi Gbit/s communications

The availability of 9GHz bandwidth around 60GHz in combination with simple modulations schemes, low-cost radio ICs and small antenna size, allows for multi Gbit/s wireless communications. In this article the potential of 60GHz wireless communications is evaluated from system, application and user point of view. Further, design challenges for 60GHz CMOS transceivers are identified. State-of-the-art designs show that short-range high-datarate radio links based on CMOS ICs can be made, potentially helped with beamforming.

Phase-Noise Mitigation at 60 GHz with a Novel Hybrid MIMO Architecture

Hybrid MIMO architectures provide a simple and effective way to implement millimeter-wave multi-user MIMO, which can deliver extremely high throughput by combining spatial multiplexing and a large bandwidth. Despite both theoretical and practical results being already available, the performance of these systems when including non-idealities is still being analyzed. In this paper we focus on phase noise originating from the multiple PLLs that causes two main problems: symbol rotation and inter-user interference. Although symbol rotation can be mitigated with conventional receiver phase noise tracking schemes, these schemes need to be jointly designed with the transmitted frame, which needs to support multi-user precoding. We analyze different receiver mitigation schemes based either on known training sequences or using blind estimation. Moreover, we propose a novel hybrid base station architecture which feeds back partial information of the status of the transmitter PLLs. Using the PLL status information, baseband compensation can be used to minimize inter-user interference improving the receiver EVM by around 5,dB.

A 54–64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between −26.5 dB and −28.8 dB in 28 nm CMOS

The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.

A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS

An 8-way phased array TRX front-end with RF phase shifting and on-chip TR switching is implemented in 28nm CMOS . The TX OP1dB and RX NF are 10dBm and 6.8dB, respectively. The active phase shifter shows less than 5° phase resolution and amplitude errors within ±0.35dB. The 9.6mm2 chip consumes 231mW in RX and 508mW in TX mode from a 0.9 V supply. When combined with PCB antennas, a ±46° scan angle is obtained with <0.4dB peak-to-peak gain ripples without calibration.