Khaled Khalaf

A low-power radio chipset in 40nm LP CMOS with beamforming for 60GHz high-data-rate wireless communication

The link budget of multi-Gb/s wireless communication systems around 60GHz improves by beamforming. CMOS realizations for this type of communication are mostly limited to either one-antenna systems [1], or beamforming ICs that do not implement all radio functions [2]. The sliding-IF architecture of [3] uses RF phase shifting, which deteriorates noise performance.

A digitally modulated 60GHz polar transmitter in 40nm CMOS

A 60GHz polar Tx prototype implemented in 40nm CMOS includes a two-stage PA with an RF-DAC, an I-Q upconversion mixer, a 60GHz LO hybrid and a digital synchronization interface. Saturated output power is approx. 10dBm, while RF output and baseband input bandwidths are 9GHz and 1.2GHz, respectively. The linear RF-DAC resolution is 5 bits. EVM degradation and spectral mask out-of-band distortion appear at input powers higher than 6dB above P-1dB. EVM is -19dB and -16dB at full rate, and -25.5dB and -22dB at reduced rates for QPSK and 16-QAM signals, respectively. The Tx consumes 75mW from 0.9V, and the core occupies 0.18mm2 of the 2.38mm2 testchip.

A 52–66GHz subharmonically injection-locked quadrature oscillator with 10GHz locking range in 40nm LP CMOS

A mm-wave subharmonically injection-locked quadrature oscillator is demonstrated in a 40nm low-power (LP) digital CMOS technology. A large locking range (10GHz), tunable over the 52-66GHz band, is achieved using transformer-coupled resonators. A simple calibration scheme is proposed that only relies on a relative power measurement of the oscillator output signal. The wide locking range, the wide tunability and the simple calibration scheme make this injection-locked quadrature oscillator design suitable for frequency synthesis in mm-wave CMOS communication systems.

Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited)

Mainstream foundries are leaping toward 14nm node and beyond. Although aggressive scaling can substantially improve digital circuit, it is very controversial for analog circuit. However, analog circuit still has to follow the scaling trend because a single chip integration offers key commercial advantages. To optimally achieve the best performance/power/cost tradeoff with deeply scaled technology nodes, there is a clear trend and paradigm shift towards digital intensive and digitally assisted transceivers. Successes of such transceivers have been proven for individual transceiver components and narrow band systems. When targeting emerging communication standards, higher carrier frequencies, further technology scaling and reconfigurable radios, required signal processing design and implementation are orders of magnitudes more challenging but potential gains are promising. Illustrated with a variety of transceivers representing emerging architectures designed for different sub-6GHz and 60GHz communication systems, we will depict key challenges that we experienced in our design and optimization process with 40nm and 28nm technology nodes.

CMOS low-power transceivers for 60GHz multi Gbit/s communications

The availability of 9GHz bandwidth around 60GHz in combination with simple modulations schemes, low-cost radio ICs and small antenna size, allows for multi Gbit/s wireless communications. In this article the potential of 60GHz wireless communications is evaluated from system, application and user point of view. Further, design challenges for 60GHz CMOS transceivers are identified. State-of-the-art designs show that short-range high-datarate radio links based on CMOS ICs can be made, potentially helped with beamforming.

A 6x-oversampling 10GS/s 60GHz polar transmitter with 15.3% average PA efficiency in 40nm CMOS

A polar TX based on a 10GSample/s RF-DAC aimed at 802.11ad applications realizes more than 30dB alias attenuation and exceeds 3GHz input bandwidth with 6x oversampling factor. The PA drain efficiency is 29.8% with a Psat of 10.8dBm. Average TX output power is 5.3dBm with 15.3% PA efficiency running QPSK at 3.3Gb/s datarate and -23.6dB EVM. Corresponding 16-QAM values are: 3.6dBm with 11.6% at 6.7Gb/s and -18.1dB EVM. The 0.18mm2 TX core in 40nm bulk-CMOS consumes 40.2mW from 0.9V.

A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitter

A complete Digital Front-End (DFE) processor for 60 GHz polar transmitter is presented. It avoids supply modulating, RF limiters, and AM detection circuits, compared to traditional analog-centric polar transmitter architectures. The front-end processor consists of i) a poly-phase Cascaded Integrator-Comb (CIC) filter for spectrum shaping; ii) parallel COordinate Rotation DIgital Computer (CORDICs) for rectangular-to-polar conversion; and iii) Power Amplifier (PA) non-linearities pre-distortion units using Look-Up Tables (LUTs). It is designed in two-phase latch-based pipeline to achieve a throughput of 4×1.76 Gsps. Implemented in a standard 28 nm CMOS technology, the DFE processor occupies 0.031 mm2 and consumes 39mW from 0.9V supply. This result outperforms previously reported architectures.

A 54–64.8 GHz subharmonically injection-locked frequency synthesizer with transmitter EVM between −26.5 dB and −28.8 dB in 28 nm CMOS

The 60 GHz frequency synthesizer presented here demonstrates a transmitter error vector magnitude (EVM) between −28.8 and −26.5 dB, from 54 to 64.8 GHz, in 28 nm digital CMOS technology. This is suitable for IEEE 802.11-2016 communications with coded datarates up to 6.4 Gb/s. Its architecture, based on subharmonic injection locking, is immune to pulling by the power amplifier. A 24 GHz phase-locked loop, designed for low phase noise, locks a 60 GHz quadrature oscillator. The phase noise of the resulting 60 GHz carrier is between −96.5 and −93.8 dBc/Hz at 1 MHz offset. The frequency synthesizer, consuming 107 mW, is integrated and demonstrated with a 60 GHz transmitter front end.

A 60GHz 8-way phased array front-end with TR switching and calibration-free beamsteering in 28nm CMOS

An 8-way phased array TRX front-end with RF phase shifting and on-chip TR switching is implemented in 28nm CMOS . The TX OP1dB and RX NF are 10dBm and 6.8dB, respectively. The active phase shifter shows less than 5° phase resolution and amplitude errors within ±0.35dB. The 9.6mm2 chip consumes 231mW in RX and 508mW in TX mode from a 0.9 V supply. When combined with PCB antennas, a ±46° scan angle is obtained with <0.4dB peak-to-peak gain ripples without calibration.