Xiaoan Zhu

Numerical study on nanowire tunnel FET with dynamic threshold operation architecture

In this paper, a nanowire tunnel field-effect transistor with dynamic threshold operation architecture (DT-NTFET) is proposed and the numerical study on its characteristics is presented. It shows that, in DT operation, the DT-NTFET can choose the threshold voltage (VT) flexibly by changing the adjust gate voltage, thus it can be applied as a multifunctional device in the future circuit design; in common mode operation, its subthreshold swing (SS) gets steeper, and its drive current is enhanced with no loss of OFF-state current.

Numerical study on effects of random dopant fluctuation in double gate tunneling FET

Impacts of random dopant fluctuations (RDFs) on the performance of an optimized double-gate (DG) tunneling FET (TFET) are studied using 3-D device simulations. The sensitivity of the TFET performance with a high-k gate dielectric to RDF is explored in this paper. Sanos approach is used to generate random doping profiles for statistical device simulation. It is found that TFET suffers from dramatic shift and fluctuations in electrical parameters (Vth, gm and SS for instance) due to RDF, thus emerging a further impact on circuit performance.

A simple leakage current model for polycrystalline silicon nanowire thin-film transistors

A simple leakage current expression is presented for the polycrystalline silicon nanowire thin-film transistors. The thermal field emission mechanism is utilized to derive the expression. The model results are compared with the experimental data at different temperatures and voltages, and good agreements are obtained.

Field-based parasitic capacitance models for 2D and 3D sub-45-nm interconnect

In the design of scaling complementary metal-oxide-semiconductor (CMOS), back-end-of-the-line (BEOL) interconnection becomes a limiting factor to circuit performance. Compact models for paratactic capacitance, which are scalable with wire geometries, are desired for circuit simulation and design. Considering both two-dimensional and three-dimensional single wire above plate, the proposed method decomposes the electric field into various regions and gives solutions for each part. The total ground capacitance is the summation of all components. The solution can be easily extended to the case of two parallel wires. Its physical base minimizes the complexity and error comparing with a traditional model fitting process. The new compact model has been verified with COMSOL simulations. It accurately predicts the capacitance for not only the nominal wire dimensions from the latest ITRS updates, but also for a wide range of other BEOL wire dimensions.

A MATLAB program for Volterra distortion analysis in CMOS switched source follower

A MATLAB program for Volterra distortion analysis of ultra high speed weakly nonlinear circuit is presented. A Volterra series method and a nodal formulation are used in this program. Approximate expressions for the transfer function, the harmonic equations and third-order intermodulation distortion equation are given respectively. Simulations based on a commercially available 65 nm CMOS process technology are performed with both the Matlab program and the SpectreRF circuit simulator. It is shown that results obtained by the MATLAB program have a consistent match with those derived from SpectreRF simulator, whereas the overall computational efficiency has been improved.

Nonlinear parameterized model order reduction method for synthesis and optimization of VLSI circuits

A parameterized model order reduction technique for nonlinear VLSI circuit system is presented in this paper, which combines the Proper Orthogonal Decomposition (POD) with the interpolation method and hence overcomes the inefficiency of POD in representing parameterized nonlinear functions. In order to capture the accuracy of the parameterized reduced model over a large range of parameter values, a training scheme is proposed to automatically select the training parameter points by the greedy sampling method. Results show that the accuracy and efficacy are improved in the proposed nonlinear parameterized reduction method.

Study on silicon window polarity of partial-SOI LDMOS power devices

The Effect of silicon window polarity on partial-SOI (partial silicon-on-insulator, PSOI) LDMOS power devices under high-voltage operation is studied. Different polarities of the silicon window in PSOI LDMOSFETs are analyzed to investigate their effects on electrical characteristics: breakdown voltage (BV) and on-resistance (Ron). In partial-SOI LDMOSFETs, the P-type silicon window is considered as a part of the substrate, while the N-type silicon window falls into the drift region, which affects the high-voltage operation of devices. The two-dimensional (2-D) simulation results show that the breakdown voltage of PSOI LDMOSFET with P-type window is higher than that of PSOI LDMOSFET with N-type window, while the on-resistance of PSOI LDMOSFET with P-type window is lower than that of PSOI LDMOSFET with N-type window.