Calogero D. Presti

A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS

A single-stage stacked field-effect transistor (FET) linear power amplifier (PA) is demonstrated using 0.28-¿m 2.5-V standard I/O FETs in a 0.13-¿m silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. With a 6.5-V supply, the measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a maximum power-added efficiency (PAE) of 47% at 1.9 GHz. Using a reverse-link IS-95 code division multiple access modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. Using an uplink wideband code division multiple access modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the adjacent channel leakage ratio requirement. The stacked-FET PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. This is the first reported stacked-FET linear PA in submicrometer SOI CMOS technology that delivers watt-level output power in the gigahertz frequency range with efficiency and linearity performance comparable to those of GaAs-based PAs.

A 25 dBm Digitally Modulated CMOS Power Amplifier for WCDMA/EDGE/OFDM With Adaptive Digital Predistortion and Efficient Power Control

A digitally modulated power amplifier (DPA) in 1.2 V 0.13 mum SOI CMOS is presented, to be used as a building block in multi-standard, multi-band polar transmitters. It performs direct amplitude modulation of an input RF carrier by digitally controlling an array of 127 unary-weighted and three binary-weighted elementary gain cells. The DPA is based on a novel two-stage topology, which allows seamless operation from 800 MHz through 2 GHz, with a full-power efficiency larger than 40% and a 25.2 dBm maximum envelope power. Adaptive digital predistortion is exploited for DPA linearization. The circuit is thus able to reconstruct 21.7 dBm WCDMA/EDGE signals at 1.9 GHz with 38% efficiency and a higher than 10 dB margin on all spectral specifications. As a result of the digital modulation technique, a higher than 20.1 % efficiency is guaranteed for WCDMA signals with a peak-to-average power ratio as high as 10.8 dB. Furthermore, a 15.3 dBm, 5 MHz WiMAX OFDM signal is successfully reconstructed with a 22% efficiency and 1.53% rms EVM. A high 10-bit nominal resolution enables a wide-range TX power control strategy to be implemented, which greatly minimizes the quiescent consumption down to 10 mW. A 16.4% CDMA average efficiency is thus obtained across a > 70 dB power control range, while complying with all the spectral specifications.

A 2.4-GHz 24-dBm SOI CMOS Power Amplifier With Fully Integrated Reconfigurable Output Matching Network

In this paper, the potential of load adaptation for enhanced backoff efficiency in RF power amplifiers (PAs) has been investigated through a 0.13-mum silicon-on-insulator (SOI) CMOS fabrication technology. The RF power performance of the adopted SOI CMOS process has been preliminarily characterized by on-wafer load-pull measurements on a custom unit power transistor. A 2.4-GHz 24-dBm 2-V SOI CMOS PA with fully integrated reconfigurable output matching network has then been designed and experimentally characterized. A significant efficiency improvement of up to 34% has been achieved through load adaptation, peak efficiency being as high as 65%. Linear operation has also been demonstrated under two-tone excitation, as a 16-dBm output power has been attained while complying with a - 40-dBc third-order intermodulation distortion specification.

Closed-Loop Digital Predistortion System With Fast Real-Time Adaptation Applied to a Handset WCDMA PA Module

A real-time adaptive digital predistortion system (RT-ADPD) for power amplifier linearization is described in this paper, featuring fast closed-loop adaptation to provide robust linearity across quickly shifting power amplifier (PA) operating conditions. The RT-ADPD system requirements, architecture, and its design methodology are analyzed in detail, with particular emphasis on the optimization of the feedback loop convergence speed and stability. A novel, compact algorithm to achieve rapid adaptation of the predistortion lookup tables, without any prior knowledge of the PA distortion characteristics, is introduced. A prototype of the RT-ADPD system is implemented using a field-programmable gate array (FPGA), and it is experimentally exploited to linearize a handset WCDMA PA module. Due to the linearization action, the PA maximum modulated output power is increased by 1.9 dB, to 30.9 dBm, and its power-added efficiency by 9%, to 48.5%, still maintaining a -40-dB ACPR at a 5-MHz offset. In addition, a true closed-loop adaptation ensures excellent PA linearity under load mismatch and other environmental variations. Indeed, ACPR is improved by up to 15 dB, below -47 dB, under 2:1 VSWR at 28 dBm. Remarkably fast adaptation speed is also demonstrated, as adequate signal fidelity is achieved within a ~50-μs time frame.

Near zero turn-on voltage high-efficiency UHF RFID rectifier in silicon-on-sapphire CMOS

A UHF RFID rectifier which turns on at near zero input voltage is demonstrated. The rectifier is fabricated in 0.25-µm silicon-on-sapphire (SOS) CMOS technology using intrinsic, near zero threshold devices. A novel improved cross-coupled bridge topology is used to minimize the leakage incurred through the use of intrinsic devices while maintaining their low power turn on characteristics. The fabricated rectifier demonstrates a peak power conversion efficiency (PCE) of 71.5% at 915MHz with a RF input of −4 dBm and a 30 kΩ load. More importantly, a PCE ≫ 30% was measured for all RF input powers between −28 and −4 dBm demonstrating state-of-the-art efficiency across a wide range of input powers.

Design Options for High Efficiency Linear Handset Power Amplifiers

Design techniques for handset power amplifiers are discussed, with emphasis on high efficiency architectures and CMOS technology. Experimental results with prototype circuits including Doherty, envelope tracking, outphasing and digital polar modulation are presented. Future design challenges are also highlighted. Index Terms — Power amplifiers, RF transmitters, wireless integrated circuit technology.

Degradation Mechanisms in CMOS Power Amplifiers Subject to Radio-Frequency Stress and Comparison to the DC Case

An in-depth study of the degradation dynamics in CMOS power amplifiers is presented. The transistor was operated at 1.9 GHz under real-world load and power conditions. Threshold voltage and sub-threshold slope were monitored as a measure of the device degradation versus stress time. Experimental evidence is provided, which demonstrates that damage severity strongly depends on the features of drain voltage and current waveforms, rather than on average dissipated power. The results of RF stress tests are compared to dc hot carrier and Fowler-Nordheim experiments. Large discrepancies are found between measurements and the quasi-static model.

A 33-dBm 1.9-GHz silicon-on-insulator CMOS stacked-FET power amplifier

A single-stage stacked-FET power amplifier (PA) is demonstrated using a 0.28-µm silicon-on-insulator (SOI) CMOS technology. To overcome the low breakdown voltage limit of MOSFETs, a stacked-FET structure is employed, where four transistors are connected in series so that their output voltage swings are added in phase. The stacked-FET PA has been designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. The measurement results show that, with a 6.5-V supply, the PA achieves a small-signal gain of 13.2 dB, a saturated output power of 33 dBm, and a maximum power-added-efficiency (PAE) of 47% at 1.9 GHz. This is the first reported stacked-FET PA in submicron SOI CMOS technology that delivers multi-Watt output power in the GHz range. It also maintains high power efficiency over a wide range of supply voltages.

A 25-dBm high-efficiency digitally-modulated SOI CMOS power amplifier for multi-standard RF polar transmitters

A single-ended digitally-modulated power amplifier (DPA) is demonstrated in a 0.13-µm 1.2-V SOI CMOS technology, to be used in a multi-standard RF polar transmitter. The amplitude modulation is done by digitally controlling the number of activated unit amplifiers whose currents are summed at the output. The DPA is designed for multi-mode multi-band functionality by avoiding frequency-selective components, except for the final-stage output matching network. The measured DPA is fully functioning and reliably delivers a 24.9-dBm peak output power at 900 MHz with a maximum power efficiency of 62.7%. It also exhibits similar high-efficiency performance for other carrier frequencies with a reconfigured matching network.

A Methodology for Fast VSWR Protection Implemented in a Monolithic 3-W 55% PAE RF CMOS Power Amplifier

In this paper, the protection of CMOS power amplifiers against load mismatch is addressed. To this purpose, a closed-loop protection circuit is proposed, which is based on a novel current-mode detection and comparison technique. The circuit allows a faster protection lock-in, by enabling peak detection and loop frequency compensation to be performed at the same circuit node, thus reducing the number of low-frequency poles and improving loop bandwidth. The effectiveness of the method is demonstrated through the implementation of a monolithic 0.25-mum 2-V CMOS power amplifier for GSM applications, which can deliver a 3-W output power with 55% overall PAE. The amplifier is able to sustain a 20:1 load VSWR at full power. Excellent RF performance and VSWR ruggedness are hence attained simultaneously, despite a simple common-emitter power stage is used. An experimental reliability assessment allowed the cognizant choice of the maximum drain-gate stress that could be tolerated. Device degradation was characterized by operating a power gain cell at RF, under real-world load and power conditions. Analysis of the degradation data enabled the design of an efficient, yet provably reliable, power amplifier.