Jonmei J. Yan

Open-Loop Digital Predistorter for RF Power Amplifiers Using Dynamic Deviation Reduction-Based Volterra Series

In this paper, we propose an efficient open-loop digital predistorter (DPD) derived from the dynamic deviation reduction-based Volterra series that allows compensation for both nonlinear distortion and memory effects induced by RF power amplifiers in wireless transmitters. In this approach, the parameters of the predistorter can be directly extracted from an offline system identification process. This eliminates the usual requirement for a closed-loop real-time parameter adaptation, which dramatically reduces the implementation complexity of the system. It is shown that a further reduction in system complexity can be achieved by applying under-sampling theory in the model extraction and utilizing parameter interpolation in the DPD implementation. Experimental results show that by utilizing this technique with only a small number of parameters, nonlinear distortion induced by the PA can be significantly reduced, as evaluated by both adjacent channel power ratio reduction and normalized root mean square error improvement. A comparison with a memoryless polynomial function based predistorter and an analysis of the impact of decresting are also presented.

Digitally Assisted Dual-Switch High-Efficiency Envelope Amplifier for Envelope-Tracking Base-Station Power Amplifiers

This paper presents a novel digitally assisted dual-switch envelope amplifier used for wideband high-efficiency envelope-tracking (ET) base-station power amplifiers (PAs). The proposed envelope amplifier comprises two switching buck converters to provide the high-power ET signal to the RF stage and a wideband linear stage to maintain the envelope signal accuracy. The control technique utilizes digital signal processing in conjunction with analog hysteretic feedback to separately control two high-efficiency switchers and thus successfully reduces power consumption of the linear stage, especially for applications requiring high peak-to-average ratio (PAPR) signals. The overall ET system was demonstrated using GaAs high-voltage HBT PAs. For a variety of signals ranging from 6.6- to 9.6-dB PAPR and up to 10-MHz RF bandwidth, the overall system power-added efficiency reached 50%-60%, with a normalized root-mean-square error below 1% and the first adjacent channel leakage power ratio of -55 dBc after digital predistortion with memory mitigation, at an average output power above 20 W and 10-dB gain.

High efficiency envelope tracking power amplifier with very low quiescent power for 20 MHz LTE

A high efficiency wideband envelope tracking power amplifier with low quiescent power is presented. The CMOS envelope amplifier has a combined linear amplifier and switching amplifier to achieve high efficiency and wider bandwidth. Quiescent power of the envelope amplifier is reduced using a source cross-coupled linear amplifier with inherently low DC power dissipation. Measurements show a power added efficiency of 45% for the envelope tracking power amplifier for 20 MHz LTE signal with 6.0 dB PAPR at 2.5 GHz at 1W output power.

Novel Technique for Wideband Digital Predistortion of Power Amplifiers With an Under-Sampling ADC

Most conventional wideband digital predistortion (DPD) techniques require the use of a very high-speed analog-to- digital converter (ADC) in the feedback path. This paper proposes a novel technique, termed under-sampling restoration digital predistortion (USR-DPD), to linearize wideband power amplifiers (PAs) with ADCs that operate at sampling rates much lower than required by Nyquist limits for the predistorted band (under-sampling ADCs). The USR processing is implemented in an iterative way to restore full-band PA output information from the under-sampled output signal, allowing memory DPD models to be successfully extracted. The USR-DPD can operate in two modes: without and with a band-limiting filter in the feedback path. In comparison with conventional DPD techniques, the requirement for ADC sampling frequency can be significantly reduced using the USR-DPD approach. Experimental tests were realized for two PAs with numerous signals (10-, 20-, 40-, and 60-MHz long-term evolution signals) using different ADC sampling frequencies. The DPD with the under-sampling ADC could achieve comparable performances to its counterpart with a full-rate ADC, while using 3-5 times lower sampling frequency, and around -50-dBc adjacent channel power ratios were achieved.

Design of a Wideband High-Voltage High-Efficiency BiCMOS Envelope Amplifier for Micro-Base-Station RF Power Amplifiers

A high-performance bipolar-CMOS-DMOS (BCD) monolithic envelope amplifier for micro-base-station power amplifiers (PAs) is presented. Measurement of the BCD high-voltage (VDD = 15 V) envelope amplifier shows an efficiency of 72% using 7.7-dB peak-to-average ratio WCDMA input signals at an average envelope amplifier output power above 3 W. A WCDMA envelope-tracking RF PA at 2.14 GHz, including a GaN field-effect transistor RF stage, has an overall drain efficiency above 51%, with a normalized power root-mean-square error below 1.2% and an adjacent channel leakage ratio of -49 dBc at 5-MHz offset using memory-effect mitigation digital pre-distortion, at an average output power above 2 W and a gain of 10 dB.

Design of a 4-W Envelope Tracking Power Amplifier With More Than One Octave Carrier Bandwidth

This paper presents a high-efficiency broadband envelope-tracking power amplifier with operation at carrier frequencies from 500 to 1750 MHz. The RF power amplifier (RFPA) is provided by a single-chip gallium-nitride (GaN) integrated circuit (IC) whose design included a broadband output match achieved by operating directly into a load resistance of 50 Ω and broadband input match achieved using a feedback network. Under single-tone excitation, the Class-AB GaN PA IC provides output power above 12 W with greater than 50% drain efficiency and more than 10-dB gain at 40-V drain bias. When placed in envelope tracking configuration, using a representative WCDMA modulated signal with 4-MHz bandwidth and 6.6-dB peak-to-average power ratio, the ET PA achieved 4 W of average output power at its peak average drain efficiency of 31% at 752 MHz (including the power dissipation of the envelope modulator). The RFPA individually was measured to have an average drain efficiency of 58.5% for the WCDMA signal. Across the 500-1750-MHz band, using the WCDMA signal, greater than 25% average drain efficiency with more than 10 dB of gain was measured.

An Envelope-Tracking CMOS-SOS Power Amplifier with 50% Overall PAE and 29.3 dBm Output Power for LTE Applications

This paper presents a CMOS envelope tracking power amplifier for LTE band-13 (782 MHz) applications. The envelope amplifier is implemented in 0.18 μm bulk CMOS process while the RF power amplifier is designed in 0.35 μm CMOS Silicon-on-Sapphire (SOS) technology. To overcome low breakdown voltage limit of MOSFETs, a stacked FET structure is used. The complete envelope tracking system achieves an overall PAE of 50% for 16 QAM, 10 MHz LTE signal with 6.6 dB peak-to-average ratio (PAPR), while delivering 29.3 dBm output power. A memory-less digital pre-distortion (DPD) is employed to linearize the overall system, which pushes ACLR down to -46.5 dBc.

RF Power Amplifier Efficiency Enhancement by Envelope Injection and Termination for Mobile Terminal Applications

An improved technique to enhance the efficiency of the linear RF power amplifiers (PAs) used in mobile terminal applications is proposed. The baseband load impedance is optimized, and the input envelope, along with the RF signal, is fed to the PA input. The resulting baseband modulation of the drain increases the saturated RF output power for a given dc power consumption. Digital predistortion is implemented to compensate for the linearity degradation. A 1.95-GHz heterojunction GaAs field-effect transistor PA, which in typical bias condition draws 100 mA from an 8.0-V supply and provides maximum power of 28 dBm for a continuous-wave input at 1.95 GHz, exhibits a significant improvement in peak power-added efficiency from 40% to 56% for a two-tone input, from 33% to 42% for an uplink WCDMA with one dedicated physical data channel (DPDCH), and from 27% to 32% for an uplink WCDMA with six DPDCHs.

Digital predistortion for envelope tracking power amplifiers

Envelope tracking seeks to achieve an optimally efficient PA by modulating the supply voltage and operating the RFPA at peak instantaneous efficiency over the majority of the waveform. However, it implies using a second power amplifier, the envelope amplifier (or envelope modulator) and it results in a nonlinear “mixing” process between the RF signal and the supply voltage. By using digital predistortion, it is possible to compensate for the system nonlinearity and achieve the desired transmitted signal. This talk will provide insights into envelope tracking systems and focus on improvements in digital predistortion beyond that used on systems with constant supply PAs.

Concurrent Dual-Band Digital Predistortion With a Single Feedback Loop

This paper proposes a compact and low-cost architecture with only a single feedback loop to implement concurrent dual-band digital predistortion (DPD) of power amplifiers (PAs). This technique is based on a new approach, down-converted carrier co-location (DC3), in conjunction with a 2-D carrier co-located memory polynomial model in PA forward modeling. The concurrent dual-band DPD models for each band can then be extracted successfully according to the forward modeling results. Experimental tests have been performed for a commercial Mini Circuits amplifier and a 120-W peak power GaN base-station PA. Different signal combinations have been tested for both balanced and unbalanced output power operations in the dual bands. The results validate that the proposed method is able to achieve linearization performances comparable to those of the conventional two parallel feedback loops based technique. Even when a nonideal feedback loop with nonflat frequency responses in the two bands is used, the new method performs well when the feedback loop is calibrated in advance. This single feedback loop based concurrent dual-band DPD architecture is a strong candidate for future broadband dual-band transmitting systems.