Can Sitik

FinFET-Based Low-Swing Clocking

A low-swing clocking methodology is introduced to achieve low-power operation at 20nm FinFET technology. Low-swing clock trees are used in existing methodologies in order to decrease the dynamic power consumption in a trade-off for 3 issues: (1) the effect of leakage power consumption, which is becoming more dominant when the process scales sub-32nm; (2) the increase in insertion delay, resulting in a high clock skew; and (3) the difficulty in driving the existing DFF sinks with a low-swing clock signal without a timing violation. In this article, a FinFET-based low-swing clocking methodology is introduced to preserve the dynamic power savings of low-swing clocking while minimizing these three negative effects, facilitated through an efficient use of FinFET technology. At scaled performance constraints, the proposed methodology at 20nm FinFET leads to 42% total power savings (clock network+DFF) compared to a FinFET-based full-swing counterpart at the same frequency (3 GHz), thanks to the dynamic power savings of low-swing clocking and 3% power savings compared to a CMOS-based low-swing implementation running at the half frequency (1.5 GHz), thanks to the leakage power savings of FinFET technology.

Timing characterization of clock buffers for clock tree synthesis

It is formidable to embed iterative simulations into the clock tree synthesis process to verify the skew and slew constraints. Instead, accurate and simple timing models for clock buffers are traditionally used so as to perform clock tree synthesis with sufficient accuracy. Two-pole RC and/or piecewise linear models accurately models the gate delay without a waveform dependency for a wide range of waveform properties. However, they unnecessarily complicate the problem for the time modeling of clock buffers where, unlike logic gates, the input and output waveform properties are similar. Look-up table-based approaches are traditionally used in order to obtain the clock buffer timing with inputs being the input slew and the output capacitance. However, the effective capacitance estimation of the highly resistive wires of sub-45nm technologies is a challenge, making it hard to identify the output capacitance. Also, the multiple or dynamically-scaled voltage levels of the current designs necessitate a costly LUT-based pre-characterization process. In this work, a timing estimation scheme for clock buffers is proposed which models both the delay and the slew as linear equations, bypassing the costly LUT characterization process. The experimental results performed with SAED 32nm buffer library show that the proposed timing model can achieve a maximum absolute value error of ≈5ps to ≈10ps for the buffer timing compared to SPICE simulations. Furthermore, the proposed timing model provides an error from 0.2% to 4.6% at different timing constraints and operating voltage levels, when used for insertion delay computation.

Enhanced level shifter for multi-voltage operation

A novel level-up shifter with dual supply voltage is proposed. The proposed design significantly reduces the short circuit current in conventional cross-coupled topology, improving the transient power consumption. Compared with the bootstrapping technique, the proposed circuit consumes significantly less area, making it more practical for ICs with a large number of supply voltages. The minimum power-delay product (PDP) for each level shifter is analyzed and compared. Worst-case corner analysis is performed for transient power, delay, and leakage power. The dependence of power and delay on input supply voltage level is also investigated for each topology. Simulation results demonstrate 43% and 36% reduction in, respectively, transient power and leakage power as compared to cross-coupled level shifter, while consuming 9.5% and 79.5% less physical area than, respectively, cross-coupled and bootstrapping techniques.

A Novel Static D-Flip-Flop Topology for Low Swing Clocking

Low swing clocking is a well known technique to reduce dynamic power consumption of a clock network. A novel static D flip-flop topology is proposed that can reliably operate with a low swing clock signal (down to 50% of the VDD) despite the full swing data and output signals. The proposed topology enables low swing signals within the entire clock network, thereby maximizing the power saved by low swing operation. The proposed flip-flop is compared with existing low swing flip-flops using a 45 nm technology node at a clock frequency of 1.5 GHz. The results demonstrate an average reduction of 38.1% and 44.4% in, respectively, power consumption and power-delay product. The sensitivity of each circuit to clock swing is investigated. The robustness of the proposed topology is also demonstrated by ensuring reliable operation at various process, voltage, and temperature corners.

A microcontroller-based embedded system design course with PSoC3

The development of a microcontroller-based system design course using the PSoC Lab Manual and customly designed project assignments are presented in this paper. Due to the natural segregation of computing blocks on these devices as digital vs. analog blocks, microcontroller-based systems can be taught in 2 terms, for digital and analog systems design separately. The presented course is designed to combine analog and digital design concepts in one single course that lasts for 10 weeks, using the PSoC3 board. The course is designed to include (i) lab tasks and (ii) weekly assignments. Based on the course syllabus, the students are assigned lab tasks following a selected lab from the PSoC3 Lab Manual each week. In addition to these selected labs from the manual, a weekly design project is assigned which cumulatively covers concepts both the current and previous weeks, in order to provide students in-depth knowledge about the microcontrollers and programmable system-on-chip boards.

Iterative skew minimization for low swing clocks

Abstract This paper presents a new methodology that implements a low swing clock tree. For low power IC design, low swing clock trees are one of the known techniques to lower the overall power dissipation through decreasing the power consumption of the clock network, while trading off the clock skew, local timing (slack) and the variation-tolerance (due to decreased noise margin). In this paper, an iterative skew minimization scheme for low swing clock trees is proposed via in-place buffer sizing considering multiple process corners. The proposed approach can preserve the power savings of the low swing clock tree implementation across multiple process corners. The effect of the decreased clock swing on the local timing is analyzed: The degradation in the timing slack is shown to be insignificant due to bounded clock slew eliminating most of the timing degradation on the clock network or the logic paths induced by decreased clock swing. The experimental results show that the proposed methodology can achieve an average of up to 11% power savings, with a skew degradation of less than 5% compared to the original full-swing clock tree, satisfying a practical skew budget. The proposed scheme is highly practical as it only performs in-place buffer sizing on the original clock tree.