Cao Liqiang

A 3D package design with cavity substrate and stacked die

Portable consumer electronics have a tremendous demand of miniaturization, high density and high performance. 3D SIP is an efficient solution to meet this requirement. This paper had presented an innovative 3D package product configured with stacked die and cavity-embedded substrate. Through hole via in the substrate provides the signal communication at a cost-effective way. This structure satisfies the high standards for mobile products packaging by reducing the package size and cost and maintaining functionality. In this paper, some details on the design concepts of the structure are introduced. Then, since the geometric configuration of the bonding wire is unusual, the electrical performance of the wire bonds of the structure is predicted by HFSS. Though the wire bond is long, simulation results shows that it is still suitable for the speed circuits below 3GHz. On the other hand, the two-step cavity effectively improves the isolation capability between different die. Moreover, the fabrication process of this structure is presented in detail to access the design. Finally, the functional test of the end products is performed and the end products work well.

The use of buried technology in microsystem packaging achieves the new type of electronic band gap

Novel two-dimensional EBG is put forward to suppress the simultaneous switching noise of electronic systems, Based on the inductance enhanced by the development of the micro system substrate embedded technology in recent years in the long-linemetal between adjacent unit cell, the novel two-dimensional EBG structure is achieved by the units lattice structure, which is made of the connection of a square metal and two metal serpentine lines. Simulation results show that the stopband bandwidth of new EBG structure labeling on capacitor is 0 ~ 8GHz (S21 ≤ -15dB)in the same parameters EBG classic.

A novel wirebond-BGA CPU package

The evolution of microprocessor packaging continues to be driven by ever increasing performance, economics and different market segment requirements. CPU evolution in performance/cost is driving the packaging technology continuously. Institute of Microelectronics, Chinese Academy of Sciences has implemented the CPU packaging in 2010. The fabricated package meets all the requirements by Loongson Company, and becomes the first fully domestically packaged CPU in China.

The hybrid method is introduced to use in suppression to synchronous switch noise in high-speed

In this paper, a novel plane of electromagnetic bandgap (EBG) structure for wideband mitigation of simultaneous switching noise (SSN) based on the modern packaging materials and embedded technology. From the simulated and measured results of the proposed EBG structure, a wideband suppression of SSN ranges from 0.1 GHz to 20GHz is achieved with a high mitigation level of -40 dB. Furthermore, the influence of the proposed power plane of EBG structure on the signal integrity (SI) is investigated in the time and frequency domains, respectively. The results show that the SI performance can be improved significantly by using differential pairs for the signals.

A novel embedded panel level package technology

Consumer and enterprise applications have precipitated an insatiable appetite for ever-increasing density, functionality, and portability requirements of active devices. Such aggressive requirements, which have challenged the viability of conventional packaging technologies, have prompted researchers and engineers to explore suitable alternatives. Garnering the attention of academia and industry is Embedded Panel Level Package. This enabling technology significantly enhances the versatility of the overall package thereby facilitating contemporary density and functionality requirements. A viable process to enable Embedded Panel Level Package would finally permit designers to incorporate all components on and inside the substrate, thus entailing a 3-D System-in-Package (SiP). In this paper, we illustrate the design, fabrication and testing of embedded MOSFET dies to exemplify the viability of this emerging technology. The impetus of this heuristic study is to develop a practical solution that is conducive to reduced manufacturing costs and truncated time-to-market product development cycles. Thus, we propose a streamlined methodology involving the simulation, optimization and fabrication of active chips embedded in organic substrates by employing a novel hybrid manufacturing process. Emphasis is placed on the simulation of thermal loading conditions and thermal-mechanical properties. It is imperative to incorporate sufficient thermal margins to ensure the viability of the fabricated embedded devices. Optimized thermal-loading and thermal-mechanical designs of the embedded MOSFET die are efficiently facilitated by numerical simulations based on finite element analyses (FEA). Finally, resistance and functional tests of the fabricated embedded MOSFET have been performed thereby demonstrating the viability of the manufacturing process for embedding active devices.

Fabrication of PN junction capacitor using SiP technology on Si-based interposer wafer

The article relates to the fabrication of embedded P-N junction capacitors, using System-in-Package (SiP) technology, on a silicon interposer wafer with Through-Silicon-Via (TSV). The P-N junction capacitors are fabricated using current micromachining technologies, including etching high aspect-ratio, three-dimensional honeycomb structure and thermal oxidation, thermal dopant diffusion, sputtering, and metallization and so on. The fabricated capacitor displays high capacitance density compared with common two-dimensional (2D) P-N junction capacitors. Tests at high frequency (10 Mhz–40 GHz) were conducted to evaluate the properties of these capacitors. Test results show that the capacitors have a high capacitance density up to 12nF/mm2 of wafer area, with reverse bias voltage of 1V, which is about 10–12 times that of 2D semiconductor capacitors, and is attributed to the increased junction area inherent in the three-dimensional via structure. These capacitors can be used for decoupling under a wide frequency range from 300 MHz to 3.2 GHz. they show a low parasitic inductance by measuring. Capacitor has a characteristic that capacitance value also keeps up constant with the increase of frequency.

Characteristics of high frequency and high density through silicon vias (TSVs)

TSV has now been a hotspot of the industry for years. Comparing with the wire-bonding, the technology populated in the last decade, Through Silicon Via (TSV) has merits of shorter wiring route, better signal integrity, larger bandwidth, lower power consumption and smaller packaging size. Undoubtedly, the TSV is treated by the industry to be the next generation of packaging solution to replace the wire-bonding. However, the TSV engineering has to conquer several difficulties, e.g. drilling technique, via filling technique, via filling material, stacking and bonding technique, and handling after the wafer thinning, etc. Therefore the standardization of the TSV still has a long way to go. This paper illustrates the initial achievement concerning with via filling material and corresponding high frequency and high density advantages that acquired by Institute of Microelectronics, Chinese Academy of Sciences.