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Featured researches published by Guo Xueping.


international conference on electronic packaging technology | 2010

Fabrication of PN junction capacitor using SiP technology on Si-based interposer wafer

Dai Fengwei; Wang Huijuan; Wang Qidong; Zhou Jing; Gao Wei; Guo Xueping; Cao Liqiang; Wan Lixi

The article relates to the fabrication of embedded P-N junction capacitors, using System-in-Package (SiP) technology, on a silicon interposer wafer with Through-Silicon-Via (TSV). The P-N junction capacitors are fabricated using current micromachining technologies, including etching high aspect-ratio, three-dimensional honeycomb structure and thermal oxidation, thermal dopant diffusion, sputtering, and metallization and so on. The fabricated capacitor displays high capacitance density compared with common two-dimensional (2D) P-N junction capacitors. Tests at high frequency (10 Mhz–40 GHz) were conducted to evaluate the properties of these capacitors. Test results show that the capacitors have a high capacitance density up to 12nF/mm2 of wafer area, with reverse bias voltage of 1V, which is about 10–12 times that of 2D semiconductor capacitors, and is attributed to the increased junction area inherent in the three-dimensional via structure. These capacitors can be used for decoupling under a wide frequency range from 300 MHz to 3.2 GHz. they show a low parasitic inductance by measuring. Capacitor has a characteristic that capacitance value also keeps up constant with the increase of frequency.


international conference on electronic packaging technology | 2010

Characteristics of high frequency and high density through silicon vias (TSVs)

Wang Qidong; Guo Xueping; Wang Huijuan; Dai Fengwei; Zhou Jing; Gao Wei; Li Jun; Cao Liqiang; Wan Lixi; Daniel Guidotti

TSV has now been a hotspot of the industry for years. Comparing with the wire-bonding, the technology populated in the last decade, Through Silicon Via (TSV) has merits of shorter wiring route, better signal integrity, larger bandwidth, lower power consumption and smaller packaging size. Undoubtedly, the TSV is treated by the industry to be the next generation of packaging solution to replace the wire-bonding. However, the TSV engineering has to conquer several difficulties, e.g. drilling technique, via filling technique, via filling material, stacking and bonding technique, and handling after the wafer thinning, etc. Therefore the standardization of the TSV still has a long way to go. This paper illustrates the initial achievement concerning with via filling material and corresponding high frequency and high density advantages that acquired by Institute of Microelectronics, Chinese Academy of Sciences.


Archive | 2013

TSV or TGV pinboard, 3D packaging and manufacture method thereof

Li Jun; Wan Lixi; Guo Xueping


Archive | 2017

Passive device integration method based on capacitor core board

Li Jun; Zhang Jing; Guo Xueping


Archive | 2017

Fan -out type packaging structure of power electronic device

Hou Fengze; Guo Xueping; Zhou Yunyan


Archive | 2017

Chip packaging structure and preparation method thereof

Guo Xueping; Hao Hu; Yu Zhongyao


Archive | 2017

High heat dissipation device package manufacturing method

Yu Zhongyao; Guo Xueping; Cao Liqiang


Archive | 2017

High heat dissipation device package structure and board manufacturing method

Yu Zhongyao; Guo Xueping; Cao Liqiang


Archive | 2017

Chip board-level packaging structure and manufacturing method

Guo Xueping; Yu Zhongyao; Cao Liqiang; Lin Tingyu; Hao Hu


Archive | 2017

Board-level embedded encapsulation structure and method for power electronic device

Hou Fengze; Guo Xueping; Zhou Yunyan

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Cao Liqiang

Chinese Academy of Sciences

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Li Jun

Chinese Academy of Sciences

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Wan Lixi

Chinese Academy of Sciences

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Wang Qidong

Chinese Academy of Sciences

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Zhou Jing

Chinese Academy of Sciences

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Dai Fengwei

Chinese Academy of Sciences

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Gao Wei

Chinese Academy of Sciences

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Wang Huijuan

Chinese Academy of Sciences

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Daniel Guidotti

Georgia Institute of Technology

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