Carlis Sánchez-Azqueta

A phase detection scheme for clock and data recovery applications

This paper presents the design and functional simulation of a new multi-level bang-bang phase detector for use in a clock and data recovery circuit (CDR). The designed phase detector provides information of the nature of the delay between its input signals in a digitised manner, establishing six levels of quantisation. To avoid the metastability that hinders the performance of traditional bang-bang phase detectors, a scheme of phase delay sensing is proposed that eliminates the need to sample the data stream close to data transitions in the locked state. Behavioural simulations are provided comparing the performance of the proposed phase detector with that of a conventional bang-bang phase detector.

A CMOS continuous-time equalizer for short-reach optical communications

This paper presents a new CMOS analog equalizer for short-reach optical communications. The circuit has been designed in a standard 0.18 µm CMOS process. The equalizer is aimed for multi-gigabit short-range applications, targeting up to 3.125 Gbps through a 50 m SI-POF. The proposed structure operates with a supply voltage of 1 V and has a power consumption of 2.5 mW.

Design criteria for loop filters in spectrum balancing technique-based adaptive equalisers

Equalisation is mandatory in modern high-speed communications systems; among the different techniques proposed in the literature, adaptive equalisation at the receiver based on the power spectrum balancing technique is the preferred solution because of its capability to take into account the varying channel characteristics and its low power requirements. This paper presents an overview of the different structure that are used in the literature, establishing measureable design criteria for the filters based on the characteristics of the channel and the equalizer filter.

CMOS receiver with equalizer and CDR for short-reach optical communications

This paper presents an optical receiver for short reach applications through low-cost plastic optical fiber. The limited bandwidth caused by the fiber and the external photodiode is compensated by a new adaptive equalizer based on the spectrum balancing technique. A clock and data recovery circuit is included that minimizes jitter and metastability using a new multi-level bang-bang architecture. The prototype, implemented in a standard 0.18-μm CMOS process, achieves 1.25 Gb/s with a power under 110 mW at only 1 V.

A 3.125 GHz four stage voltage controlled ring oscillator in 0.18 CMOS

In this paper, a 3.125 GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18 µm CMOS process with a 1.8 V supply. Behavioural simulations predict an 18% tuning range for the oscillator, with a −91 dBc/Hz phase noise at a 1 MHz offset. Its power consumption has been simulated to be only 12.6 mW.

Bang-bang phase detector model revisited

The operation of bang-bang phase detectors (BBPDs) in clock and data recovery circuits (CDRs) is typically modeled in terms of the phase difference between their inputs; however, this approach is not sufficient to describe their dynamic behavior completely. This paper introduces a more comprehensive model of the operation of BBPDs that takes into account phase as well as frequency differences between their inputs. Numerical simulations of the operation of a CDR have been carried out to evaluate the validity of the model.

A 1.25 Gb/s fully integrated optical receiver for SI-POF applications

This paper presents the design of a 1.25 Gb/s fully integrated BiCMOS optical receiver for short reach applications through low-cost step index plastic optical fiber. The limited bandwidth caused by the fiber is compensated by a continuous-time equalizer. A low noise transimpedance amplifier with some peaking overcomes the limitation introduced by the integrated photodiode. A post-amplifier has been included to generate the required digital output levels. The design achieves 1.25 Gb/s through 50 m SI-POF with a power consumption of 148 mW and a sensitivity of -16.4 dBm for a BER of 10-12. Simulation results are provided.