Guillermo Royo

CMOS transimpedance amplifier with controllable gain for RF overlay

In this paper, a fully-differential transimpedance amplifier (TIA) with controllable transimpedance for use in RF overlay downstream communication systems is presented. It consists of a shunt-shunt feedback transimpedance amplifier with transimpedance and open loop gain control. The transimpedance amplifier is intended for 47 MHz to 870 MHz subcarrier multiplexed RF signals with a 18 dBΩ transimpedance gain control range. The TIA, designed in a CMOS 180 nm technology, dissipates 27 mW from a supply voltage of 1.8 V. The input-referred noise current is lower than 6 pA/√Hz to allow an optical input power from -6 to +2 dBm.

Continuous-Time Linear Equalizer for Multigigabit Transmission Through SI-POF in Factory Area Networks

This letter presents a new complimentary metal-oxide-semiconductor analog continuous-time equalizer aimed to compensate the limited frequency response of step-index polymer optical fiber (SI-POF), a transmission medium very attractive for industrial applications as factory automation and process control networks because of its cost and immunity to electromagnetic interference. The structure overcomes the limitations of the most widely used continuous-time equalizer, the degenerated differential pair, for 1-V supply voltage. The linear equalizer has been proved for multigigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The prototype consumes 2.7 mW.

Programmable Low-Power Low-Noise Capacitance to Voltage Converter for MEMS Accelerometers

In this work, we present a capacitance-to-voltage converter (CVC) for capacitive accelerometers based on microelectromechanical systems (MEMS). Based on a fully-differential transimpedance amplifier (TIA), it features a 34-dB transimpedance gain control and over one decade programmable bandwidth, from 75 kHz to 1.2 MHz. The TIA is aimed for low-cost low-power capacitive sensor applications. It has been designed in a standard 0.18-μm CMOS technology and its power consumption is only 54 μW. At the maximum transimpedance configuration, the TIA shows an equivalent input noise of 42 fA/Hz at 50 kHz, which corresponds to 100 μg/Hz.

Lightweight ciphers based on chaotic Map - LFSR architectures

In this paper, we propose and analyze two different stream ciphers based on a Skew Tent Map and a Modified Logistic Map respectively. In order to improve the randomness of these systems, a single method for increasing the period length of the generated sequences has been applied. The results prove that the randomness of these systems can be severally increased by using this method, making these systems suitable for secure communications.

1-V continuous-time linear equalizer for up to 2 Gb/s over 50-m SI-POF

In this paper, we present a new CMOS analog continuous-time linear equalizer. The proposed structure overcomes some of the limitations due to the low supply voltage of the most widely used continuous-time equalizer, the degenerated differential pair. The prototype has been tested for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The proposed linear equalizer was designed in a cost-effective 90-nm CMOS process. The system is fed with a single supply voltage of 1 V and consumes 2.7 mW.

Fully-differential transimpedance amplifier for reliable wireless communications

Abstract The demand of mobile and wireless devices has been continuously growing over the last years, driving the development of new wireless communication systems to provide high data capacity and good accessibility at high data transmission rates. Wireless communication systems must also show high immunity to interference, and in this context distributed systems formed by several remote antenna units (RAU) fed by multi-mode fibers are becoming the preferred solution. At high transmission data rate increases, issues brought by the variability in the fabrication of the circuits and ambient conditions (PVT variations) become more important, and it is necessary to design the systems to minimize their effect. In this work, a fully-differential transimpedance amplifier (TIA) for the receiver in a RAU is presented. The TIA has been designed in a 180-nm RF CMOS technology with a 1.8-V voltage supply and it achieves a bandwidth of 2.5 GHz with a power consumption of 26 mW. To overcome the effect of PVT variations, the TIA features a programmable transimpedance of 20-dB linear-in-dB programmable transimpedance, also increasing the input dynamic range to improve the overall linear range of operation.

Transimpedance amplifier with programmable gain and bandwidth for capacitive MEMS accelerometers

In this work, a capacitance-to-voltage converter based on a fully-differential transimpedance amplifier (TIA) with programmable gain and bandwidth for MEMS accelerometers is presented. It is aimed for a differential surface-micromachined comb-finger capacitive accelerometer, but can be used in many other capacitive sensor applications. The TIA has been designed in a 180-nm CMOS technology and it achieves a minimum equivalent input noise of 42 fA/√Hz at 50 kHz, which corresponds to an acceleration noise of 100 μg/√Hz.

Design of a low-power quadrature LC-VCO in 65 nm CMOS

This paper presents the design of a low-power quadrature oscillator for frequency synthesis in intermediate frequency over fiber (IFoF) applications at the lower-end of the 5G WiFi band. It is formed by two class-B LC-VCOs connected in a cross-coupled configuration. A cascaded architecture has been used for the coupling stages in order to stabilize the oscillation by minimizing bimodal oscillation and the back coupling between the two coupled LC-VCO stages. The prototype has been designed in a standard 65 nm process fed at 0.9 V instead of the nominal 1.2 V. It achieves a tuning range from 4.9GHz to 5.75 GHz, and a phase noise figure of −110.5 dBc/Hz at 1 MHz from the carrier at the maximum oscillating frequency of 5.75 GHz, for which the oscillation amplitude is close to 300 mV. Excluding the output buffer implemented for testing, the proposed quadrature oscillator consumes only 1.8mW, which yields a FoM of 182.7dB.