Carol Boye

E-beam inspection for combination use of defect detection and CD measurement

This paper proposes a combination use of e-beam inspection (EBI) for defect detection and CD Uniformity (CDU) measurement. The experiments are based on 14nm FinFET device manufactured on SOI substrate. A 5nm pixel size is utilized to perform hot spot inspection on SRAM pattern and N/P FET pattern after gate etching, spacer formation, and SiGe epitaxy process respectively. CDU measurement results match well with process split in gate etching and spacer formation process. Protrusion defect is detected after SiGe epitaxy process, and a dependency between protrusion defects with the thickness of spacer is found.

Process Window Centering for 22 nm lithography

Process window centering (PWC) is an efficient methodology to validate or adjust and center the overall process window for a particular lithography layer by detecting systematic and random defects. The PWC methodology incorporates a defect inspection and analysis of the entire die that can be automated to provide timely results. This makes it a good compromise between focus exposure matrix, where centering is based only on critical dimension measurements of a few specific structures and process window qualification which provides very detailed defect inspection and analysis, but is more time consuming for lithography centering. This paper describes the application of the PWC methodology for 22 nm lithography centering in IBMs Albany, NY, and East Fishkill, NY, development facilities using KLA-Tencors 28xx brightfield defect inspection system.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Wafer line productivity optimization in a multi-technology multi-part-number fabricator

Successful semiconductor manufacturing is driven by wafer-level productivity. Increasing profits by reducing manufacturing cost is a matter of optimizing the factors contributing to wafer productivity. The major wafer productivity components are chips per wafer (CPW), wafer process or fabricator yield (WPY) and wafer final test (WFT) or functional yield. CPW is the count of product chips fitting within the useable wafer surface, and is dependent upon the chip size, dicing channel (kerf) space, and wafer-field size. WPY yield is the percentage of wafers successfully exiting the line; losses include scrap for broken wafers and failed-wafer specifications. WFT yield is the percent of chips that meet all final parametric functional electrical test specifications. Thus, the total wafer level productivity (GCPW) is described by GCPW=CPW/spl middot/WPY/spl middot/WFT. IBMs Vermont fabricator is one of the few in the industry that manufactures DRAMs, SRAMs, microprocessors, ASICs, custom logic, mixed signal, and foundry products, all on the same production floor. The product portfolio spans 12 base technologies across four photolithographic generations from 0.8 /spl mu/m to 0.225 /spl mu/m, with development of 0.18 /spl mu/m. This also encompasses 40 major process flows and over 4000 active part numbers. Such staggering complexity has motivated IBM to consider all possible optimization of these productivity components. This paper describes some of the techniques that have been deployed to achieve this goal.

Assessing EUV mask defectivity

This paper assesses the readiness of EUV masks for pilot line production. The printability of well characterized reticle defects, with particular emphasis on those reticle defects that cause electrical errors on wafer test chips, is investigated. The reticles are equipped with test marks that are inspected in a die-to-die mode (using DUV inspection tool) and reviewed (using a SEM tool), and which also comprise electrically testable patterns. The reticles have three modules comprising features with 32 nm ground rules in 104 nm pitch, 22 nm ground rules with 80 nm pitch, and 16 nm ground rules with 56 nm pitch (on the wafer scale). In order to determine whether specific defects originate from the substrate, the multilayer film, the absorber stack, or from the patterning process, the reticles were inspected after each fabrication step. Following fabrication, the reticles were used to print wafers on a 0.25 NA full-field ASML EUV exposure tool. The printed wafers were inspected with state of the art bright-field and Deep UV inspection tools. It is observed that the printability of EUV mask defects down to a pitch of 56 nm shows a trend of increased printability as the pitch of the printed pattern gets smaller - a well established trend at larger pitches of 80 nm and 104 nm, respectively. The sensitivity of state-of-the-art reticle inspection tools is greatly improved over that of the previous generation of tools. There appears to be no apparent decline in the sensitivity of these state-of-the-art reticle inspection tools for higher density (smaller) patterns on the mask, even down to 56nm pitch (1x). Preliminary results indicate that a blank defect density of the order of 0.25 defects/cm2 can support very early learning on EUV pilot line production at the 16nm node.

EUVL Reticle Defectivity Evaluation

Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous study [1] were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and discussed together with a defect classification.

High-throughput critical dimensions uniformity (CDU) measurement of two-dimensional (2D) structures using scanning electron microscope (SEM) systems

In this paper, we tested a novel methodology of measuring critical dimension (CD) uniformity, or CDU, with electron beam (e-beam) hotspot inspection and measurement systems developed by Hermes Microvision, Inc. (HMI). The systems were used to take images of two-dimensional (2D) array patterns and measure CDU values in a custom designated fashion. Because this methodology combined imaging of scanning micro scope (SEM) and CD value averaging over a large array pattern of optical CD, or OCD, it can measure CDU of 2D arrays with high accuracy, high repeatability and high throughput.

Use of 22 nm Litho SEM Non-visual Defect Data as a Process Quality Indicator

This paper proposes that the non-visual defect rate for Litho layers is an indicator of the quality of the process up to and including Litho. “Non-visual” (NV) defects are those detected by optical defect inspection systems but not re-detected by the SEM review tool. The defects are occurring either on or below the surfaces of the films deposited immediately prior to lithography, or buried within the actual lithographic films. Rather than ignore the non-visual data obtained during defect inspection post lithography, the NV rate can be used as a quality indicator to trigger immediate action for root cause determination. This paper presents a new strategy for responding to Litho SEM NV defects based on a detailed study of the origin of these defects.

Use of 22 nm Litho SEM non-visual defect data as a process quality indicator

This paper proposes that the non-visual defect rate for Litho layers is an indicator of the quality of the process up to and including Litho. “Non-visual” (NV) defects are those detected by optical defect inspection systems but not re-detected by the SEM review tool. The defects are occurring either on or below the surfaces of the films deposited immediately prior to lithography, or buried within the actual lithographic films. Rather than ignore the non-visual data obtained during defect inspection post lithography, the NV rate can be used as a quality indicator to trigger immediate action for root cause determination. This paper presents a new strategy for responding to Litho SEM NV defects based on a detailed study of the origin of these defects.

Optimizing a 32nm development fab's HOL defect pareto using iDO and eADC

This paper presents a methodology for optimizing a fab defect pareto for 32nm Health of Line (HOL). HOL involves running a selected product as a means of generating defect baseline paretos and electrical test for key process sectors. Optimizing HOL pareto consists of increasing the capture of key yield limiting defects and minimizing the capture of non yield limiting defects. This was achieved by implementing smart binning (iDO) on the BF inspection system in conjunction with auto defect classification (eADC) on the SEM review tool.