Cédric Durand

In-Plane Silicon-On-Nothing Nanometer-Scale Resonant Suspended Gate MOSFET for In-IC Integration Perspectives

A 14-MHz in-plane nanoelectromechanical resonator based on a resonant-suspended-gate (RSG) MOSFET principle and integrated in a front-end process is demonstrated. The devices are in-plane flexural vibration mode beams (L = 10 mum, w = 165 nm, and h = 400 nm) with 120-nm gaps. This letter details the design and process flow fabrication steps. Then, the electrical device characteristics are demonstrated, comprising static and dynamic studies around the resonant frequency. Devices enable the comparison of a pure capacitive detection with the RSG-MOSFET-based detection on the same component, showing a 4.3-dB-huge peak. Due to its output signal amplification and in-IC integration potentialities, the RSG-MOSFET-based detection is ideal for any type of nanoelectromechanical structure displacement detection.

Ultra-Sensitive Capacitive Detection Based on SGMOSFET Compatible With Front-End CMOS Process

Capacitive measurement of very small displacement of nano-electro-mechanical systems (NEMS) presents some issues that are discussed in this article. It is shown that performance is fairly improved when integrating on a same die the NEMS and CMOS electronics. As an initial step toward full integration, an in-plane suspended gate MOSFET (SGMOSFET) compatible with a front-end CMOS has been developed. The device model, its fabrication, and its experimental measurement are presented. Performance obtained with this device is experimentally compared to the one obtained with a stand-alone NEMS readout circuit, which is used as a reference detection system. The 130 nm CMOS ASIC uses a bridge measurement technique and a high sensitive first stage to minimize the influence of any parasitic capacitances.

Characterization of IN-IC integrable in-plane nanometer scale resonators fabricated by a silicon on nothing advanced CMOS technology

The paper reports on in-plane nanometer scale resonators fabricated on 8 inch industrial tools, with a process based on the advanced CMOS Front End Silicon On Nothing Technology. The aim is to propose totally integrated time reference functions realized by small size NEMS resonators. The measurement set-up, simulation and experimental results in the range of 100 MHz are presented. Environmental issues such as temperature and pressure influence on the resonator behavior are also investigated. Results are discussed and compared with analytic calculation, finite element and electrical simulations with good agreement. Work in progress focuses on improving the f.Q product, detection by the use of integrated MOSFET transistors, low voltage operation and in-IC integration.

Measurement of Nano-Displacement Based on In-Plane Suspended-Gate MOSFET Detection Compatible with a Front-End CMOS Process

The first front-end CMOS co-integration based on the lateral SGMOSFET presented in this paper demonstrates the benefit of a co-integration approach for NEMS devices. Performance using this device is compared to that obtained with a standalone ASIC. The next step will consist of replacing equivalently the input transistor of the ASIC cascode structure by the SGMOSFET.

Integration of multi-standard front end modules SOCs on high resistivity SOI RF CMOS technology

RF front end modules (FEMs) are currently realized using a variety of technologies. However, since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning FEM integration on silicon [1]. In this quest, SOI technology has already addressed two key blocks, the antenna switch and the power amplifier. In this paper, we will focus our investigation on high performance passive functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, balun, harmonic filter, diplexer and directional coupler have been achieved in a 130 nm SOI CMOS technology. Measured performances are clearly competitive with most commercially available Integrated Passive Device (IPD) solutions, which paves the way of FEM silicon SOCs.

Innovative 8-shaped inductors integrated in an advanced BiCMOS technology

As integrated inductors are a key component for RF circuits, these devices are mainly highlighted because of an imposing size and disturbing radiations. This article focuses on two innovative 8-shaped inductors presenting size reduction and low radiation capability. 8-shaped devices are compared to octagonal inductors by the way of measurements and simulations. 8-shaped inductors, even if presenting slightly lower electrical performances (lower size but lower quality factor), show interesting coupling reduction, with improvements from 7 to 20 dB depending of inductor design and orientation. Future works will consist of optimizing 2/3-turn 8-shaped layouts and test designs in circuit applications.

Enablement of advanced silicon photonics optical passive library design leveraging silicon based RF passive development methodology

Silicon photonics technology emerged as a promising solution to address the technical challenges related to 100 Gb/s and 400 Gb/s optical link. Enabling the development of silicon photonics products requires the development of optical passive libraries integrated within conventional CAD tools used in the CMOS design flow. The optimization and modeling of silicon photonics optical passive is therefore a key point that can be addressed by leveraging methodologies that have been previously set up for optimizing RF passive in CMOS and BiCMOS technologies. In this paper, the relevance of such an approach is evaluated: the combination of FDTD electromagnetic simulations and a Design Of Experiments (DOE) prototyping have been used for optimizing scalable Grating Couplers (GCs) targeting Wavelength-Division Multiplexing applications (WDM). The obtained models for the GC have been successfully qualified experimentally.

Sub-THz source integrated in industrial silicon Photonic technology targeting high data rate wireless applications

Leveraging the performances offered by advanced CMOS processes, silicon technologies enable today the development of cost effective millimeter-wave (mmW) applications (60 GHz wireless link is a good example). In order to achieve higher data rates (> 10 Gb/s), we can now think about moving to sub-THz frequencies in order to take advantage of wider frequency bands. In this context, the development of Si based sub-THz sources will be a key enabler. In this paper, using a beat-note of two lasers, we evaluate the performance of an industrial Si Photonics PIN Photo Diode as a sub-THz source. An output power of ∼ −28 dBm is obtained at 200 GHz.

Sub-THz source integrated in low-cost Silicon Photonic technology targeting 40 Gb/s wireless links

Following the race for transmitting/receiving at higher data rate, we can observe intensive development of millimeter-wave wireless systems in low-cost CMOS technology. Data rates above 10 Gb/s are now targeted in order to address the data traffic bottleneck of backhaul links for the 5G wireless network. To do so, antenna-systems operating at sub-THz frequencies show great potential, leveraging high-performance photonic technology. This paper presents a sub-THz source based on a SiGe PIN photodiode integrated in low-cost Silicon Photonic technology. Using a laser beat-note, the photodiode delivers an output power ranging from −20 dBm to −29 dBm between 125 and 325 GHz. Leveraging this wide operating band, data rate exceeding 40 Gb/s can be targeted.

Integration of cellular front end modules on advanced high resistivity SOI RF CMOS technology

Since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning front end module (FEM) integration on silicon [1]. In this quest, SOI technology has emerged as the technology of choice [2] since the antenna switch and the power amplifier (PA) have been successfully integrated on SOI [3, 4]. In this paper, we will focus our investigation on high performance passive functions in order to demonstrate the capability of SOI CMOS technology to integrate the whole FEM. To do so, balun, harmonic filter, diplexer and directional coupler have been achieved in a 130 nm SOI CMOS technology. Measured performances are clearly competitive with most commercially available Integrated Passive Device (IPD) solutions, which paves the way of FEM silicon SOCs.