Hussein Fakhoury

A 65 nm CMOS versatile ADC using time interleaving and ΣΔ modulation for multi-mode receiver

High performances wideband Analog to Digital Converter (ADC) remains a bottleneck to realize software and cognitive radio receivers. Time Interleaved Sigma-Delta (TIΣΔ) architecture is a good candidate to increase the bandwidth of the data converters with the lowest hardware complexity compared to other solutions using parallel sigma-delta modulators. This paper proposes a reconfigurable 4 channels TIΣΔ using the novel GMSCL (General Multi Stage Closed Loop) sigma-delta architecture and a new digital processing reducing considerably the hardware complexity. The sigma-delta modulators have been designed using switched-capacitor technique and implemented with STMicroelectronis 65 nm CMOS technology. Three different scenarios are possible : the first one for GSM standard clocked at 26 MHz and consumes 2.59 mW, the second one for UMTS/DVB-T standards clocked at 208 MHz and consumes 46 mW and the last one for WiFi/WiMax standards clocked at 208 MHz and consumes 92 mW. The total circuit die area is equal to 3 mm2. The digital filtering was validated and synthesized in a 1.2 V, 65 nm CMOS process using VHDL language. For a clock rate of 208 MHz, the evaluated die area is 0.115 mm2.

Statistical analysis of noise in broadband and high resolution ADCs

The estimation of mismatch-induced errors between the channels of a Time-Interleaved ADC is crucial for implementing an efficient calibration method. This step is often done with the assumption that all the noise sources have a white gaussian distribution. In this paper we analyze the statistical properties of noise components in wideband ADCs in terms of Probability Density Function (PDF) and Power Spectral Density (PSD) and discuss some conditions of whiteness.

A LP/HP UMTS/GSM ΣΔ ADC suited for a Zero-IF/Low-IF receiver

This paper presents the design of a reconfigurable Delta Sigma Analog to Digital Converter (ADC). Its main degree of liberty is the choice of the noise shaping among low pass and high pass. This reconfiguration parameter allows it to be adapted for both the Low-IF and the Zero-If receiver architectures. The ADC is GSM/UMTS compliant. It was designed in a 1.2 V 65 nm CMOS process. Electrical simulation results showed a SNDR of 84 dB for the GSM mode with a Low-IF frequency of 19.2 MHz and a SNDR of 77.4 dB for the UMTS at DC.

Generalized multi-stage closed loop sigma delta modulator

This paper presents a new high order cascade sigma delta modulator called GMSCL. It uses first and/or second order modulator with unity signal transfer function in each stage and a global feedback to lower the sensitivity to circuit imperfections, to relax the output swing and gain requirements of amplifiers and to avoid digital prefiltering in the quantization error cancellation logic. The zeros of the noise transfer function are optimized to improve the modulator performance. This topology is thus very suitable for wideband low voltage applications. Behavioral simulations demonstrate the high efficiency of the proposed topology comparing to existing cascade topologies.

A low-power ΣΔ ADC optimized for GSM/EDGE standard in 65-nm CMOS

A ΣΔ ADC with both Signal Transfer Function (STF) and Noise Transfer Function (NTF) optimized for GSM/EDGE application is presented. A direct-feedforward single-loop filter is used to improve linearity of the modulator at low supply voltage. From the edge of the signal bandwidth to over 1MHz of band, measured STF is flat and in-band ripple is less than 0.01dB. Clocked @ 26MHz the modulator achieves 82dB dynamic-range, 80dB peak SNR, −85dB peak THD, 88dBc peak SFDR. Implemented in 65-nm CMOS, it consumes 1.74mW from the 1.2V supply and occupies an active die area of 0.081mm2 (395µm×205µm) without voltage references.

A 65nm CMOS EDGE/UMTS/WLAN tri-mode four-channel time-interleaved ΣΔ ADC

A four-channel time-interleaved ΣΔ analog-to-digital-converter for EDGE/UMTS/WLAN tri-mode zero-IF receiver is presented. The number of time-interleaved channels, the clock rate and the order of the modulators are programmable. The former adapts the conversion bandwidth to the selected standard while the two last are set to reach dynamic range specifications. Each channel uses a Global Multi-Stage Closed-Loop ΣΔ modulator which is a novel cascade 2-2 topology. A Sample-And-Hold circuit is used at the front-end of the ADC to reduce the clock skew issue inherent to time-interleaved converters. The prototype chip was implemented in a 1.2V 65nm CMOS process using metal-insulator-metal capacitors. Simulated dynamic range is 80dB/80dB/50dB in 135KHz/2MHz/12.5MHz respectively. The number of active channels in EDGE/UMTS/WLAN mode is one, two and four respectively which leads to a power consumption of 3.1mW/55.2mW/110.4mW. Clocked at 208MHz, the analog front-end exhibits an SFDR less than −90dB over 2MHz bandwidth and consumes 12mW. The total active die area is 2.2mm².

A high dynamic range stacked ADCs receiver for long wavelength radio astronomy observations

We introduce the design and simulation results of a stacked ADCs architecture that allows the implementation of a wideband and high dynamic range radio astronomy receivers. This work focus on the capabilities of this architecture to make a significant dynamic range enhancement compared to single-ADC based receivers. A detailed analytical analysis of the power consumption shows that this architecture stretches the bandwidth of the receiver up to 100 MHz while being very power efficient. Furthermore, its excellent time-frequency resolution makes this architecture very attractive for spatial exploration missions.

Statistical analysis of harmonic distortion in a differential bootstrapped sample and hold circuit

The bootstrap technique is known to increase the linearity of Sample and Hold (S/H) circuit by reducing the input signal dependency of the transistor-switch resistance. But some nonlinearities remain due to parasitic capacitances, mobility degradation and back gate effect resulting in a second order harmonic spurious which can be reduced with a differential architecture. However mismatch between channels limits this technique. In this paper, we provide a general framework to analyze the residual nonlinearity in bootstrapped S/H. Statistical laws are also provided converting harmonic distortion specifications into matching requirements for differential sampling and therefore provide key rules for S/H designers.

A novel dynamic element matching technique suited for high pass ΔΣ ADCs

This paper presents a novel dynamic element matching technique (DEM) suited for high pass (HP) Delta Sigma (ΔΣ) modulators. It is based on transforming the high pass filtering behavior of classical DEM algorithms into a low pass behavior to make them adapted for HP ΔΣ modulators. The proposed technique is demonstrated for the data weight averaging (DWA) algorithm at the system level and the electrical level using a 65 nm CMOS process. The achieved performances in terms of SFDR and SNDR are similar to the performances of classical low pass (LP) ΔΣ modulators employing regular DWA. Moreover the required additional complexity is very low : just 8 simple switches and some digital gates.

A low power RC time constant auto-tuning circuit for RC-integrators in high linearity continuous-time delta sigma modulators

This paper presents the design of a low power RC time constant tuning circuit for high linearity 5th order continuous time Delta Sigma modulator used in LTE-A application with 40 MHz bandwidth. This auto-tuning system contains an analog integrator, a voltage comparator, and a digital tuning engine performed by a clock generator, a register and a counter which generate a control word that sets a programmable capacitors bank to obtain an RC time constant accuracy better than ±2%. It resolves process variations issues which could result in up to ±30% of RC time constant uncertainty and degrade the Delta Sigma modulators SNDR. The system has been designed in a 65 nm CMOS technology with 1.2 V supply voltage and power consumption is less than 200 μW.