Chan-kyung Kim

CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

This paper presents novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In the proposed temperature sensor, the temperature dependency of poly resistance is used to generate a temperature-dependent bias current, and a ring oscillator driven by this bias current is employed to obtain the digital code pertaining to on-chip temperature. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on bandgap reference. The proposed CMOS temperature sensor was fabricated with an 80nm 3-metal DRAM process, which occupies extremely small silicon area of only about 0.016mm^2 with under 1@mW power consumption for providing 0.7^oC effective resolution at 1 sample/s processing rate. This result indicates that as much as 73% area reduction was obtained with improved resolution as compared to the conventional temperature sensor in mobile DRAM.

7.4 A covalent-bonded cross-coupled current-mode sense amplifier for STT-MRAM with 1T1MTJ common source-line structure array

In this paper, we present a sensing scheme for STT-MRAM with 1T1MTJ common SL structure array: covalent-bonded cross-coupled current-mode sense amplifier (CBSA). The CBSA can fit in conventional DRAM array architecture and use two normal cells in adjacent BLs, one for storing data “1” and the other for storing data “0”, for generating reference currents for CBSA. There are 64 CBSAs in a row of 8k cells, where one CBSA and two references BLs are shared by adjacent 128 BLs. STT-MRAM cell is directly accessed instead of page opening as in DRAM. By introducing CBSAs as sensing schemes, read-access time can be reduced to under 10ns with strong robustness against wide random variations of MTJ cell resistances with a small TMR.

3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions

The advance of DRAM manufacturing technology slows down, whereas the density and performance needs of DRAM continue to increase. This desire has motivated the industry to explore emerging Non-Volatile Memory (e.g., 3D XPoint) and the high-density DRAM (e.g., Managed DRAM Solution). Since such memory technologies increase the density at the cost of longer latency, lower bandwidth, or both, it is essential to use them with fast memory (e.g., conventional DRAM) to which hot pages are transferred at runtime. Nonetheless, we observe that page transfers to fast memory often block memory channels from servicing memory requests from applications for a long period. This in turn significantly increases the high-percentile response time of latency-sensitive applications. In this paper, we propose a high-density managed DRAM architecture, dubbed 3D-XPath for applications demanding both low latency and high capacity for memory. 3D-XPath DRAM stacks conventional DRAM dies with high-density DRAM dies explored in this paper and connects these DRAM dies with 3D-XPath. Especially, 3D-XPath allows unused memory channels to service memory requests from applications when primary channels supposed to handle the memory requests are blocked by page transfers at given moments, considerably increasing the high-percentile response time. This can also improve the throughput of applications frequently copying memory blocks between kernel and user memory spaces. Our evaluation shows that 3D-XPath DRAM decreases high-percentile response time of latency-sensitive applications by ~30% while improving the throughput of an I/O-intensive applications by ~39%, compared with DRAM without 3D-XPath.

Study on DHP temperature effect in PSPI exposure process

PSPI has been applied to the end-fab process for better efficiency. However, it causes process time to increase, which can be a serious problem in the photo process. Excessive exposure time results in lower efficiency and lower productivity as well. It is also blamed for a damage of expensive equipment lens. Existing countermeasures have yet to clear those problems. As an alternative, DHP temperature control is expected to reduce exposure time by adjusting the hardness of PSPI. Consequently, exposure time per shot can be sharply reduced, enhancing productivity of photo process where many shots are repeatedly exposed to a wafer.