Sang-beom Kang

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB/S and maximum write throughput of 4.64MB/S with a 1.8V supply.

A 0.1-

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal times2 write and can be increased to ~2.67 MB/s with times16 write. Endurance and retention characteristics are measured to be 107 cycles and ten years at 99 degC

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A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18 /spl mu/m CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30/spl deg/C.

1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.

A 0.18 /spl mu/m 3.0 V 64 Mb non-volatile phase-transition random-access memory (PRAM)

The three-dimensionally alternating integration of stackable logic devices with memory cells represents a revolutionary approach to the fabrication of extremely high density memory devices. Conventional silicon-based memory devices face impending limits if they are progressively scaled toward smaller-sized features. Here, we present a high-density memory architecture that utilizes electronically active oxide thin-film transistors (TFTs) combined with memory elements such as vertical NAND and resistive random access memory devices. High-mobility [~μsaturation of 20 cm2/(eV·s)] oxide TFTs with amorphous Hf-In-Zn-O performs fairly well as a decoder, a driver, a sense amplifier, and a latch, and the core elements that are required for 3-D logic circuits. With these logic circuit elements, memory density can be considerably increased up to tens of terabits due to the significantly reduced interconnection lines and logic circuit areas in the bottom silicon layer. This approach can serve as a useful strategy for the development of high-density memory devices.

Enhanced write performance of a 64 Mb phase-change random access memory

A 256Mb PRAM featuring synchronous burst read operation is developed. Using a charge-pump system, write performance is characterized at 1.8V supply. Measured initial read access time and burst-read access time are 62ns and 10ns, respectively. The maximum write throughput is 3.3MB/S

Three-Dimensional Integration Approach to High-Density Memory Devices

A 64Mb Mobile S/sup 3/RAM was designed with stacked single-crystal thin film transistor (SSTFT) cell using 80nm SRAM technology to overcome chip size penalty of conventional 6T-SRAM with improved performance. For 1.3V operation, word line (WL) and cell Vcc were pumped simultaneously using selective dual pumping scheme (SDPS). Access time of 49.2ns was achieved at 1.3V supply voltage. Multi cell burn-in scheme (MCBS) and standby current (ISB1) repair scheme enhanced the yield for the high density products.