Hyung-Rok Oh

A 90 nm 1.8 V 512 Mb Diode-Switch PRAM With 266 MB/s Read Throughput

A 512 Mb diode-switch PRAM has been developed in a 90 nm CMOS technology. The vertical diode-switch using the SEG technology has achieved minimum cell size and disturbance-free core operation. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are proposed. The 512 Mb PRAM has achieved read throughput of 266 MB/s through the proposed schemes. The write throughput was 0.54 MB/s in internal x2 write mode, and increased to 4.64 MB/s with x16 accelerated write mode at 1.8 V supply.

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB/S and maximum write throughput of 4.64MB/S with a 1.8V supply.

A 0.1-

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal times2 write and can be increased to ~2.67 MB/s with times16 write. Endurance and retention characteristics are measured to be 107 cycles and ten years at 99 degC

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A non-volatile 64 Mb phase-transition RAM is developed by fully integrating a chalcogenide alloy GST (Ge/sub 2/Sb/sub 2/Te/sub 5/) into 0.18 /spl mu/m CMOS technology. This alloy is programmed by resistive heating. To optimize SET/RESET distribution, a 512 kb sub-core architecture, featuring meshed ground line, is proposed. Random read access and write access for SET/RESET are 60 ns, 120 ns and 50 ns, respectively, at 3.0 and 30/spl deg/C.

1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.