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Dive into the research topics where Dipak Kumar Kole is active.

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Featured researches published by Dipak Kumar Kole.


international conference on vlsi design | 2008

On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set

Hafizur Rahaman; Dipak Kumar Kole; Debesh K. Das; Bhargab B. Bhattacharya

Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Newer technologies like ion trapping or nuclear magnetic resonance are required to emulate quantum gates. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely, single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. In this paper, it is shown that in an (n times n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate yields an easily testable design, which admits a universal test set of size (n +1) that detects all SMGFs, RGFs, and PMGFs in the circuit.


asian test symposium | 2007

Optimum Test Set for Bridging Fault Detection in Reversible Circuits

Hafizur Rahaman; Dipak Kumar Kole; Debesh K. Das; Bhargab B. Bhattacharya

Testing of bridging faults in a reversible circuit is investigated in this paper. The intra-level single bridging fault model is considered here, i.e. any single pair of lines, both lying at the same level of the circuit, may be assumed to have been logically shorted in order to model a defect. For an (n X n) reversible circuit with d levels realized with simple Toffoli gates, the time complexity of the test generation procedure is O(nd2 log2n). A test set of cardinality O(d log2n) is found to be sufficient for testing all such detectable faults. A minimal test set can also be easily derived by using the concept of test equivalence.


Computers & Electrical Engineering | 2011

Fault diagnosis in reversible circuits under missing-gate fault model

Hafizur Rahaman; Dipak Kumar Kole; Debesh K. Das; Bhargab B. Bhattacharya

This article presents a novel technique for fault detection as well as fault location in a reversible combinational circuit under the missing gate fault model. It is shown that in an (nxn) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k-CNOT gate, yields an easily testable design, which admits a universal test set (UTS) of size (n+1) that detects all single missing-gate faults (SMGFs), repeated-gate faults (RGFs), and partial missing-gate faults (PMGFs) in the circuit. Furthermore, storage of only one vector (seed) of the UTS is required; the rest can be generated by n successive cyclic bit-shifts from the seed. For fault location under the SMGF model, a technique for identifying the faulty gate is also presented that needs application of a single test vector, provided the circuit is augmented with some additional observable outputs.


international symposium on electronic system design | 2010

Optimal Reversible Logic Circuit Synthesis Based on a Hybrid DFS-BFS Technique

Dipak Kumar Kole; Hafizur Rahaman; Debesh K. Das; Bhargab B. Bhattacharya

Logic synthesis with reversible circuits has received considerable interest in the light of advances recently made in quantum computation. In this paper, we propose an improved technique for synthesizing reversible circuits based on a combined depth-first search (DFS) and breadth-first search (BFS) algorithm. A method based on DFS alone may often take a long time to converge, whereas, a BFS based method requires a large amount of memory for designing a circuit of moderate complexity. To strike a balance between these two approaches, we propose a hybrid DFS-BFS based synthesis algorithm that reduces the computation time compared to the DFS method and requires less space compared to the BFS method, while optimizing the cost of the circuit. Synthesis results on several reversible benchmark circuits have been reported.


International Journal of Computer Applications | 2012

Automatic Brain Tumor Detection and Isolation of Tumor Cells from MRI Images

Dipak Kumar Kole; Amiya Halder

Brain Tumor Detection refers to the problem of delineating tumorous tissues from MRI images for the purpose of medical diagnosis and surgical planning. The process uses tumor characteristics in images, such as sizes, shapes, locations and intensities for the isolation of the tumor which depends on manual tracing by experts. This paper proposes automatic brain tumor detection and isolation of tumor cells from MRI images using a genetic algorithm (GA) based clustering method, intensity based asymmetric map and region growing technique.


asian test symposium | 2010

Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits

Dipak Kumar Kole; Hafizur Rahaman; Debesh K. Das; Bhargab B. Bhattacharya

— Logic synthesis of reversible circuits has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate fault (MMGF), have been found to be more suitable for modeling defects in quantum k-CNOT gates. This article presents an efficient algorithm to derive an optimal test set (OTS) for detection of multiple missing-gate faults in a reversible circuit implemented with k-CNOT gates. It is shown that the OTS is sufficient to detect all single missing-gate faults (SMGFs) and all detectable repeated gate faults (RGFs). Experimental results on some benchmark circuits are also reported.


Archive | 2014

Detection of Downy Mildew Disease Present in the Grape Leaves Based on Fuzzy Set Theory

Dipak Kumar Kole; Arya Ghosh; Soumya Mitra

Agriculture has a significant role in economy of the most of the developing countries. A significant amount of crops are damaged in every year due to fungi, fungus, bacteria, Phytoplasmas, bad weather etc. Grapes are one of the most widely grown fruit crops in the world with significant plantings in India. Grapes are used in the production of wine, brandy, or non-fermented drinks and are eaten fresh or dried as raisins. Sometimes grape plants are affected by downy mildew, a serious fungal disease. Therefore, farmers try to detect the stage of the disease in plant at an early stage so that they can take necessary steps in order to prevent the disease from spreading to others parts of the fields. This article presents a novel technique for detection of downy mildew disease present in the grape leaves based on fuzzy importance factor. The proposed technique uses some digital image processing operations and fuzzy set theory concept. We experimented on thirty one diseased and non-diseased images and got 87.09% success. The experimental results reveal that the proposed technique can effectively detect the present of downy mildew disease in the grape leaves.


asian test symposium | 2014

Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method

Bappaditya Mondal; Dipak Kumar Kole; Debesh K. Das; Hafizur Rahaman

Reversible logic synthesis has received considerable attention in the light of advances recently made in quantum computation. Implementation of a reversible circuit is envisaged by deploying several special types of quantum gates, such as k-CNOT. Although the classical stuck-at fault model is widely used for testing conventional CMOS circuits, new fault models, namely single missing-gate fault (SMGF), repeated-gate fault (RGF), partial missing-gate fault (PMGF), and multiple missing-gate faults (MMGF), are likely to be more suitable for modeling defects in quantum k-CNOT gates. This work proposes an algorithm for deriving the test set for the detection of all single missing gate faults in a reversible circuit implemented with k-CNOT gates. Instead of deriving test set directly for the detection of missing gate faults, a Boolean generator is developed by Boolean difference method to derive the test set and to detect all the single missing gate faults of a reversible circuit. Experimental results on some benchmark circuits are also reported.


advances in computing and communications | 2012

An Optimized S-Box for Advanced Encryption Standard (AES) Design

Oyshee Brotee Sahoo; Dipak Kumar Kole; Hafizur Rahaman

This work presents an optimized Substitution Box (S-Box) for Advanced Encryption Standard (AES) design. The S-Box is one of the most important components of AES. During SubByte transformation, the eight bit input is substituted by eight bit output using the S-Box. S-Box is constructed by composing two transformation - multiplicative inverse in Galois Field GF(28) followed by an affine transformation. The S-Box is the most time and power consuming component of AES Algorithm. In this paper, we have modified the affine transformation and tried to reduce the time complexity of AES. The time consumption for AES S-Box is decreased by the proposed affine transformation.


advances in computing and communications | 2012

Implementation of AES Algorithm in UART Module for Secured Data Transfer

Debjani Basu; Dipak Kumar Kole; Hafizur Rahaman

This work proposes the application of Advanced Encryption Standard (AES) algorithm in Universal Asynchronous Receiver Transmitter (UART) module for secure transfer of data. The proposed architecture implements AES-128 algorithm that encrypts the data before transmission through UART transmitter and decrypts after receiving the data at UART receiver module. In this work, we present the AES-128 encryption and decryption circuit using iterative architecture. The design has a clock generator circuit which provides the different clock frequencies to different sub modules. The complete design is described in Verilog Hardware Description Language (HDL) and is functionally verified using Xilinx ISE 9.1i software. It takes 47.2msec to transmit 128 bit encrypted data and 36.7msec to receive decrypted data on a Xilinx xc2vp70-7ff517 device. All the blocks of the proposed architecture are designed using FPGA technology.

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Hafizur Rahaman

Indian Institute of Engineering Science and Technology

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Bappaditya Mondal

Indian Institute of Engineering Science and Technology

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Chandan Giri

Indian Institute of Engineering Science and Technology

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Dhiman Mondal

Jalpaiguri Government Engineering College

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Apurba Sarkar

Indian Institute of Engineering Science and Technology

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Chandan Bandyopadhyay

Indian Institute of Engineering Science and Technology

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Diptesh Majumdar

Indian Institute of Technology Guwahati

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