Chang-Min Jeon

A 45-nm logic compatible 4Mb-split-gate embedded flash with 1M-cycling-endurance

For the first time, 4Mb split-gate type embedded flash is developed in 45-nm technology with 1M cycling endurance for mass production of various applications. Process integration is designed for logic compatibility, minimizing shift of logic device characteristics so that existing IPs can be used. By process optimization of triple-gate flash architecture, high speed operation (write time of 25us and erase operation of less than 2ms) and robust reliability (1M cycle, 150 □ retention) are achieved.

A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)

The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.

High-speed and logic-compatible split-gate embedded flash on 28-nm low-power HKMG logic process

We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um2) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) and robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture and scaling of word-line (WL) transistor. New type of high-voltage transistor with LDD-first scheme is applied to enable further scaling of decoder block in Flash IP. Digital-Vdd (1.0V) read operation is used by lowering threshold voltage (Vth) of HV transistor without sacrificing break-down during Flash P/E operation. By using module process concept, the existing RF and logic IP is reused without modification.

Highly Scalable 2nd-Generation 45-nm Split-Gate Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance

We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns random access time, 25us write time and less than 2ms erase operation) and robust reliability (1M cycle, 20 retention) are achieved. It has been successfully verified in range of 1Mb up to 16Mb density flash IPs.