Hyo-sang Lee

A 130-nm 0.9-V 66-MHz 8-Mb (256K /spl times/ 32) local SONOS embedded flash EEPROM

In a 0.13-/spl mu/m CMOS logic compatible process, a 256K /spl times/ 32 bit (8 Mb) local SONOS embedded flash EEPROM was implemented using the ATD-assisted current sense amplifier (AACSA) for 0.9 V (0.7 /spl sim/ 1.4 V) low V/sub CC/ application. Read operation is performed at a high frequency of 66 MHz and shows a low current of typically 5 mA at 66-MHz operating frequency. Program operation is performed for common source array with wide I/Os (/spl times/32) by using the data-dependent source bias control scheme (DDSBCS). This novel local SONOS embedded flash EEPROM core has the cell size of 0.276 /spl mu/m/sup 2/ (16.3 F/sup 2//bit) and the program and erase time of 20 /spl mu/s and 20 ms, respectively.

A 45-nm logic compatible 4Mb-split-gate embedded flash with 1M-cycling-endurance

For the first time, 4Mb split-gate type embedded flash is developed in 45-nm technology with 1M cycling endurance for mass production of various applications. Process integration is designed for logic compatibility, minimizing shift of logic device characteristics so that existing IPs can be used. By process optimization of triple-gate flash architecture, high speed operation (write time of 25us and erase operation of less than 2ms) and robust reliability (1M cycle, 150 □ retention) are achieved.

High-speed and logic-compatible split-gate embedded flash on 28-nm low-power HKMG logic process

We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um2) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) and robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture and scaling of word-line (WL) transistor. New type of high-voltage transistor with LDD-first scheme is applied to enable further scaling of decoder block in Flash IP. Digital-Vdd (1.0V) read operation is used by lowering threshold voltage (Vth) of HV transistor without sacrificing break-down during Flash P/E operation. By using module process concept, the existing RF and logic IP is reused without modification.

Highly Scalable 2nd-Generation 45-nm Split-Gate Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance

We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns random access time, 25us write time and less than 2ms erase operation) and robust reliability (1M cycle, 20 retention) are achieved. It has been successfully verified in range of 1Mb up to 16Mb density flash IPs.