Seok-Ha Lee

Future 1T1C FRAM technologies for highly reliable, high density FRAM

Recent 32 Mb FRAM technologies realizing 0.25 /spl mu/m/15F2 cell are introduced and key integration technologies for future highly reliable, high density FRAM are suggested. Etchless capacitor technology and MOCVD PZT technology are the promising solutions for realizing future highly reliable, high density FRAM beyond 32 Mb density.

Improvement of crosstalk on 5M CMOS image sensor with 1.7x1.7μm2 pixels

Crosstalk of CMOS Image Sensor (CIS) causes degradation of spatial resolution, color mixing and leads to image noise. Crosstalk consists of spectral, optical and electrical components, but definition of each component is obscure and difficult to quantify. For the first time, quantifiable definition of each component is proposed to perform crosstalk analysis in this paper. Contribution of each component to the total crosstalk is analyzed using opto-electrical simulation. Simulation is performed with an internally developed 2D finite difference time domain (FDTD) simulator coupled to a commercial device simulator. Simulation domain consists of set of four pixels. Plane wave propagation from micro-lens to the photodiode is analyzed with FDTD and the optical simulation result is transformed into the photo-current in the photodiode using electrical simulation. The total crosstalk consists of 43% of spectral crosstalk, 14% of optical cross talk, and 43% of electrical crosstalk at the normal incident light. Spectral crosstalk can be suppressed through careful selection of color filter materials with good selectivity of color spectrum. Characteristics of crosstalk and photosensitivity show contrary trend to one another as a function of color filter thickness. Therefore, the crosstalk target is fixed and simulation is performed to determine the minimum color filter thickness that satisfies the crosstalk target. By color filter material and thickness optimization, 10% increase in photosensitivity and 7% decrease spectral crosstalk were obtained. Electrical crosstalk showed 11% and 9% improvement through applying to new implantation process and stacking multi-epi layer on the p-type substrate, respectively.

The Features and Characteristics of 5-mega CMOS Image Sensor with Topologically Unique 1.7/spl m/m~1.7/spl mu/m Pixels

CMOS image sensor (CIS) of 5-mega pixel density has been successfully developed with the smallest pixels (1.7mumtimes1.7mum) ever made. The newly introduced unique pixel architecture brought excellent optical symmetry and high electron capacity. Degradation of sensitivity and cross-talk can be suppressed with the optimization of the optical structure through proper color filter material and reduction of total aspect ratio (vertical stack height/pixel pitch) with Cu back end of line (BEOL)

Dedicated process architecture and the characteristics of 1.4 μm pixel CMOS image sensor with 8M density

A 1.4 μm-pitch pixel of CMOS image sensor, which is the smallest to date, has been successfully developed and integrated into 8M density for the first time. To overcome the crucial degradation of the saturation charge and sensitivity, a novel photodiode structure extended under transfer gate and an elaborate optical design including very thin tungsten pixel routing with 65 nm-grade design rules are introduced, which result in enhanced electrical and optical performance.

1/2.5" 8 mega-pixel CMOS Image Sensor with enhanced image quality for DSC application

Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application

The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels

5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed

Three Dimensional CMOS Image Sensor Cell Simulation and Optimization

In this work, we present the results of three-dimensional CMOS image sensor cell simulation. Electrical characteristics of the device are represented comprehensively. The methodology, describing saturation, charge-voltage conversion, and image lag of a CIS cell in a single simulation analysis, is expected to play a key role in future CMOS image sensor cell development.