Chang-Sub Lee

80 nm 512M DRAM with enhanced data retention time using partially-insulated cell array transistor (PiCAT)

An 80 nm 512M DDR DRAM with partially-insulated cell array transistor (PiCAT) was fabricated. Si/SiGe epitaxial growth and selective SiGe etch process were used to form PiOX (Partially-Insulating OXide) under source and drain of the cell transistor. Using these technologies, partial-SOI (Silicon-On-Insulator) structure could be realized with excellent structural and electrical advantages on bulk Si wafer. Self-limited shallow junction under source/drain and halo doping effect at the channel region were formed by PiOX. With PiCAT, junction leakage current and SCE (Short Channel Effect) were reduced, and excellent data retention time was obtained.

The Effect of Field Oxide Recess on Cell

We present our study on the effect of field oxide recess on cell-programming-speed uniformity of nand flash cell memory. Due to the short distance between the control gate and the shallow-trench-isolation (STI) edge, the control-gate voltage generates uniform distribution of an electric field on the STI edge and provides strong immunity to fabrication process variation in cell programming. Therefore, the optimized field oxide recess offers an inherently narrower cell V TH distribution, fastening multilevel-cell programming speed while minimizing the floating-gate interference. Experimental results on 63-nm cell arrays show that the cell V TH distribution is reduced by 18% or more as field oxide recess increases.

V_{\rm TH}

We introduce a novel CMOS transistor fabrication technique using damascene gate with local channel implantation (LCI). This transistor has a benefit to reduce the resistance of source/drain extension (SDE) localizing the severe blanket channel implantation under the channel only. It can reduce the junction capacitance as well. This process technology is reliable for the formation of channel length down to 22 nm with smooth gate line edge roughness. Some unique processes for the small transistor fabrication are also introduced. The 22-nm nMOSFET with 0.9 nm RTO is achieved with the drive current of 930 /spl mu/A//spl mu/m for the off-current of 100 nA//spl mu/m at 1.0 V. Hot carrier reliability exceeding 10 years for 1.0 V operation is also obtained.

Distribution of nand Flash Cell Arrays

The cell string current of NAND flash memory is very small due to large resistance from the cells connected in series. In this paper, scaling effects on the cell current are analyzed for 70/60/50 nm NAND flash technologies using 3-dimensional TCAD simulation. The geometrical and process parameters are varied and their effects are quantified. It is identified that the coupling ratio has the most significant impact on the cell current and the LDD engineering is more relevant for higher cell current

A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

In this article, we evaluated the structural merits of a partially insulated MOSFET (PiFET), for ultimate scaling of planar MOSFETs, through simulation and fabrication. The newly fabricated PiFET showed outstanding short channel effect (SCE) immunity and off-current characteristics over the conventional MOSFET, resulting from a self-induced halo region, self-limiting S/D shallow junction, and reduced junction area due to PiOX layer formation. Thus, the PiFET can be an attractive alternative for ultimate scaling of planar MOSFETs.

3-dimensional analysis on the cell string current of NAND flash memory

We introduce new phenomena that show turn-on at back-side for Vertical NAND (V-NAND) with back-insulator and propose a new method to analyze the trap of back-interface related to the phenomena. Back-side traps have been analyzed with the back-gate structure [1]. However, V-NAND has no back-gate structure, so its difficult to observe traps. With RTN method we proposed, its possible for us to observe back-side traps.

Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions

We present a new field effect mechanism on IGIDL in NAND flash strings. According to the proposed 5-terminal GIDL model, special care should be taken to optimize the biasing levels of inhibit scheme. Suggested incremental biasing scheme can be one of the solutions for reducing critical field that enhances boosting efficiency and maximizes memory yields.

A new approach for trap analysis of vertical NAND flash cell using RTN characteristics

By stressing via-incorporated interconnect structures, we demonstrate for the first time the accelerated deterioration of leakage reliability relative to conventional biased-thermal-stressing of Cu line/space modules. Electric field analyses confirm said finding, invoking the need to correspondingly adjust the reliability testing criteria to ensure the most conservative lifetime projection. Two important collateral consequences include leakage aggravation with Ar plasma treatment prior to barrier metal deposition and bias direction dependence of intra-via or line-via reliability.

A new GIDL phenomenon by field effect of neighboring cell transistors and its control solutions in sub-30 nm NAND flash devices

In this paper, the degradation characteristics of high-voltage (HV) p-type MOSFETs are investigated during negative unipolar ac stress on the gate electrode. The threshold voltage under ac stress is shifted gradually by both the negative-bias temperature-instability mechanism and Fowler-Nordheim degradation. We qualitatively analyze the degradation characteristics of HV p-type MOSFETs under ac stress, and observe the threshold voltage saturation for HV p-type MOSFETs at long ac stress. Based on the effects of temperature and duty cycles, we offer a suitable model of degradation saturation after long ac stress, which is caused by interface trap saturation and recovery during pulse delay timing, which is dependent on thermal activation energy.

Re-defining reliability assessment per new intra-via Cu leakage degradation

One of the most important performances of NAND flash memory is reliability characteristics, such as program/erase cycling and data retention. Tunnel oxide quality is essential to the reliability and it is well known that tunnel oxide degradation during FN (Fowler-Nordheim) stress is due to the oxide trap and interface trap generation. It is believed that trapping mainly occurs where tunnel oxide is locally thin. For example, conventional SAP (self-aligned poly) process with shallow trench isolation, tunnel oxide at active edge is necessarily thinner than active channel. In this paper, we proposed a new process scheme to fabricate optimized tunnel oxide thickness varying from active center to edge, and we confirmed the improvement of reliability characteristics such as Vth shift and interface trap density during endurance cycling